linux-toradex.git/arch/mips/kernel/smp-mt.c, branch v4.3.1

mips: fix up obsolete cpu function usage.

2015-03-05T04:55:06+00:00

Thanks to spatch, plus manual removal of "&*".  Then a sweep for
for_each_cpu_mask => for_each_cpu.

Signed-off-by: Rusty Russell 
Cc: Ralf Baechle 
Cc: Kevin Cernekee 
Cc: Florian Fainelli 
Cc: linux-mips@linux-mips.org

MIPS: smp-mt,smp-cmp: Enable all HW IRQs on secondary CPUs

2015-01-16T12:02:40+00:00

Commit 18743d2781d0 ("irqchip: mips-gic: Stop using per-platform mapping
tables") in v3.19-rc1 changed the routing of IPIs through the GIC to go
to the HW0 IRQ pin along with the rest of the GIC interrupts, rather
than to HW1 and HW2 pins.

This breaks SMP boot using the CMP or MT SMP implementations because HW0
doesn't get unmasked when secondary CPUs are initialised so the IPIs
will never interrupt secondary CPUs (nor any other interrupts routed
through the GIC).

Commit ff1e29ade4c6 ("MIPS: smp-cps: Enable all hardware interrupts on
secondary CPUs") fixed this in advance for the CPS SMP implementation by
unmasking all hardware interrupt lines for secondary CPUs, so lets do
the same for the CMP and MT implementations.

Fixes: 18743d2781d0 ("irqchip: mips-gic: Stop using per-platform mapping tables")
Signed-off-by: James Hogan 
Cc: Andrew Bresticker 
Cc: Qais Yousef 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9025/
Signed-off-by: Ralf Baechle

MIPS: Move gic.h to include/linux/irqchip/mips-gic.h

2014-11-24T06:44:59+00:00

Now that the MIPS GIC irqchip lives in drivers/irqchip/, move
its header over to include/linux/irqchip/.

Signed-off-by: Andrew Bresticker 
Cc: Daniel Lezcano 
Cc: Thomas Gleixner 
Cc: Jason Cooper 
Cc: Paul Burton 
Cc: Qais Yousef 
Cc: John Crispin 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8129/
Signed-off-by: Ralf Baechle

MIPS: Move GIC to drivers/irqchip/

2014-11-24T06:44:54+00:00

Move GIC irqchip support to drivers/irqchip/ and rename the Kconfig
option from IRQ_GIC to MIPS_GIC to avoid confusion with the ARM GIC.

Signed-off-by: Andrew Bresticker 
Acked-by: Jason Cooper 
Reviewed-by: Qais Yousef 
Tested-by: Qais Yousef 
Cc: Thomas Gleixner 
Cc: Jeffrey Deans 
Cc: Markos Chandras 
Cc: Paul Burton 
Cc: Jonas Gorski 
Cc: John Crispin 
Cc: David Daney 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/7812/
Signed-off-by: Ralf Baechle

MIPS: smp-mt: Fix link error when PROC_FS=n

2014-08-01T16:32:02+00:00

Commit d6d3c9afaab4 (MIPS: MT: proc: Add support for printing VPE and TC
ids) causes a link error when CONFIG_PROC_FS=n:

arch/mips/built-in.o: In function `proc_cpuinfo_notifier_init':
smp-mt.c: undefined reference to `register_proc_cpuinfo_notifier'

This is fixed by adding an ifdef around the procfs handling code
in smp-mt.c.

Signed-off-by: James Hogan 
Reported-by: Markos Chandras 
Reviewed-by: Markos Chandras 
Cc: Ralf Baechle 
Cc: linux-mips@linux-mips.org
Cc:  # >= 3.15
Patchwork: https://patchwork.linux-mips.org/patch/7244/
Signed-off-by: Ralf Baechle

MIPS: SMP: Remove plat_smp_ops cpus_done method.

2014-05-27T09:06:42+00:00

Nothing was using the method and there isn't any need for this hook.  This
leaves smp_cpus_done() empty for the moment.

As suggested by Paul Bolle .

Signed-off-by: Ralf Baechle

MIPS: smp-mt: Use common GIC IPI implementation

2014-03-31T16:17:12+00:00

Rather than duplicating the GIC IPI send function, share the one already
used by CONFIG_MIPS_CPS & CONFIG_MIPS_CMP.

Signed-off-by: Paul Burton 
Cc: linux-mips@linux-mips.org
Cc: Paul Burton 
Patchwork: https://patchwork.linux-mips.org/patch/6653/
Signed-off-by: Ralf Baechle

MIPS: MT: proc: Add support for printing VPE and TC ids

2014-03-31T16:17:12+00:00

And there are more CPUs or configurations that want to provide special
per-CPU information in /proc/cpuinfo.  So I think there needs to be a
hook mechanism, such as a notifier.

This is a first cut only; I need to think about what sort of looking
the notifier needs to have.  But I'd appreciate testing on MT hardware!

Signed-off-by: Ralf Baechle 
Cc: Markos Chandras 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6066/

MIPS: GIC: Send IPIs using the GIC

2014-01-22T19:18:57+00:00

If GIC is present, then use it to send IPIs between the cores.
Using GIC for IPIs is simpler and is usable for multicore
systems compared to the existing way of doing IPIs where all VPEs
had to be disabled for another VPE to access the Cause register
in one of the TCs and enable all the VPEs back.

Signed-off-by: Steven J. Hill 
Signed-off-by: Markos Chandras 
Signed-off-by: John Crispin 
Patchwork: http://patchwork.linux-mips.org/patch/6040/

MIPS: MT: Mark existing TCs as present

2014-01-22T19:18:56+00:00

According to Documentation/cpu-hotplug.txt, the cpu_present_mask should
contain all the CPUs which are present in the system. Therefore, all the TCs
currently present in the system should be marked as 'present' even if they
will never be brought online.

Signed-off-by: Markos Chandras 
Signed-off-by: John Crispin 
Patchwork: http://patchwork.linux-mips.org/patch/6039/