linux-toradex.git/arch/mips/kernel/traps.c, branch v2.6.32.31 Linux kernel for Apalis and Colibri modules MIPS: Rewrite sysmips(MIPS_ATOMIC_SET, ...) in C with inline assembler 2009-09-17T18:07:49+00:00 Ralf Baechle ralf@linux-mips.org 2009-09-17T00:25:05+00:00 f1e39a4a616cd9981a9decfd5332fd07a01abb8b This way it doesn't have to use CONFIG_CPU_HAS_LLSC anymore. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
This way it doesn't have to use CONFIG_CPU_HAS_LLSC anymore.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: Move Cavium CP0 hwrena impl bits to cpu-feature-overrides.h 2009-06-17T10:06:31+00:00 David Daney ddaney@caviumnetworks.com 2009-05-13T22:59:56+00:00 4bb1a1089e321d685967032497f4363081eab3a9 We had an ugly #ifdef for Cavium Octeon hwrena bits in traps.c, remove it to mach-cavium-octeon/cpu-feature-overrides.h Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
We had an ugly #ifdef for Cavium Octeon hwrena bits in traps.c, remove
it to mach-cavium-octeon/cpu-feature-overrides.h

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: Allow CPU specific overriding of CP0 hwrena impl bits. 2009-06-17T10:06:31+00:00 David Daney ddaney@caviumnetworks.com 2009-05-13T22:59:55+00:00 fbeda19f82aa07082d2e1607a9f5114141dae2ac Some CPUs have implementation dependent rdhwr registers. Allow them to be enabled on a per CPU basis. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Some CPUs have implementation dependent rdhwr registers.  Allow them
to be enabled on a per CPU basis.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: Use BUG_ON() where possible. 2009-03-30T12:49:44+00:00 Ralf Baechle ralf@linux-mips.org 2009-03-30T12:49:44+00:00 b72b7092f8f5f0729cc9f0868997351f21dbc5cd Based on original patch by Stoyan Gaydarov <stoyboyker@gmail.com> which missed a few places. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Based on original patch by Stoyan Gaydarov <stoyboyker@gmail.com> which
missed a few places.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: R2: Fix problem with code that incorrectly modifies ebase. 2009-03-23T22:38:05+00:00 Chris Dearman chris@mips.com 2009-03-20T22:33:55+00:00 9fb4c2b9e06c0a197d867b34865b113a47370bd5 Commit 566f74f6b2f8b85d5b8d6caaf97e5672cecd3e3e had a change that incorrectly modified ebase. This backs out the lines that modified ebase. In addition, the ebase exception vector is now allocated with correct alignment and the ebase register updated according to the architecture specification. Based on original patch by David VomLehn <dvomlehn@cisco.com>. Signed-off-by: David VomLehn <dvomlehn@cisco.com> Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Commit 566f74f6b2f8b85d5b8d6caaf97e5672cecd3e3e had a change that
incorrectly modified ebase. This backs out the lines that modified
ebase.
In addition, the ebase exception vector is now allocated with correct
alignment and the ebase register updated according to the architecture
specification.

Based on original patch by David VomLehn <dvomlehn@cisco.com>.

Signed-off-by: David VomLehn <dvomlehn@cisco.com>
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: Read watch registers with interrupts disabled. 2009-01-30T21:32:58+00:00 David Daney ddaney@caviumnetworks.com 2009-01-05T23:29:58+00:00 8bc6d05b481aa7dc79c81b8ffac0da755e149643 If a context switch occurred between the watch exception and reading the watch registers, it would be possible for the new process to corrupt their state. Enabling interrupts only after the watch registers are read avoids this race. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
If a context switch occurred between the watch exception and reading the
watch registers, it would be possible for the new process to corrupt their
state.  Enabling interrupts only after the watch registers are read avoids
this race.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: R2: Fix broken installation of cache error handler. 2009-01-30T21:32:58+00:00 Ralf Baechle ralf@linux-mips.org 2009-01-28T18:48:23+00:00 42fe7ee31ff904b2419f02864938966c8f0b6edc Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: For Cavium OCTEON set hwrena and lazily restore CP2 state. 2009-01-11T09:57:21+00:00 David Daney ddaney@caviumnetworks.com 2008-12-11T23:33:23+00:00 f9bb4cf37ad3f7dec63abc5db688dd1e9df0056c If on Cavium, be aware of cop2 and hwrena during do_cpu(). Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
If on Cavium, be aware of cop2 and hwrena during do_cpu().

Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: Switch FPU emulator trap to BREAK instruction. 2008-10-30T14:44:34+00:00 Ralf Baechle ralf@linux-mips.org 2008-10-28T17:38:42+00:00 ba3049ed4086737dab200b6087138a4b8e06915d Arguably using the address error handler has always been ugly. But with processors that handle unaligned loads and stores in hardware the current mechanism ceases to work so switch it to a BREAK instruction and allocate break code 514 to the FPU emulator. Yoichi Yuasa provided a build fix for CONFIG_BUG=n. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> 
Arguably using the address error handler has always been ugly.  But with
processors that handle unaligned loads and stores in hardware the
current mechanism ceases to work so switch it to a BREAK instruction and
allocate break code 514 to the FPU emulator.

Yoichi Yuasa provided a build fix for CONFIG_BUG=n.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
MIPS: Consider value of c0_ebase when computing value of exception base. 2008-10-30T14:44:33+00:00 David Daney ddaney@caviumnetworks.com 2008-10-24T00:56:35+00:00 566f74f6b2f8b85d5b8d6caaf97e5672cecd3e3e It just so happens to be zero on all currently supported systems so this hasn't bitten yet ... [Ralf: Original patch from Cavium; handling of set_uncached_handler() and de-ifdef'ed trap_init() implementation by me.] Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
It just so happens to be zero on all currently supported systems so this
hasn't bitten yet ...

[Ralf: Original patch from Cavium; handling of set_uncached_handler() and
de-ifdef'ed trap_init() implementation by me.]

Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>