<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-toradex.git/arch/mips/kernel/unaligned.c, branch v5.10-rc2</title>
<subtitle>Linux kernel for Apalis and Colibri modules</subtitle>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/'/>
<entry>
<title>uaccess: add force_uaccess_{begin,end} helpers</title>
<updated>2020-08-12T17:57:59+00:00</updated>
<author>
<name>Christoph Hellwig</name>
<email>hch@lst.de</email>
</author>
<published>2020-08-12T01:33:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=3d13f313ce4c34c524ccc37986fe77172f601ff3'/>
<id>3d13f313ce4c34c524ccc37986fe77172f601ff3</id>
<content type='text'>
Add helpers to wrap the get_fs/set_fs magic for undoing any damange done
by set_fs(KERNEL_DS).  There is no real functional benefit, but this
documents the intent of these calls better, and will allow stubbing the
functions out easily for kernels builds that do not allow address space
overrides in the future.

[hch@lst.de: drop two incorrect hunks, fix a commit log typo]
  Link: http://lkml.kernel.org/r/20200714105505.935079-6-hch@lst.de

Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
Signed-off-by: Andrew Morton &lt;akpm@linux-foundation.org&gt;
Acked-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
Acked-by: Mark Rutland &lt;mark.rutland@arm.com&gt;
Acked-by: Greentime Hu &lt;green.hu@gmail.com&gt;
Acked-by: Geert Uytterhoeven &lt;geert@linux-m68k.org&gt;
Cc: Nick Hu &lt;nickhu@andestech.com&gt;
Cc: Vincent Chen &lt;deanbo422@gmail.com&gt;
Cc: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;
Cc: Palmer Dabbelt &lt;palmer@dabbelt.com&gt;
Link: http://lkml.kernel.org/r/20200710135706.537715-6-hch@lst.de
Signed-off-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add helpers to wrap the get_fs/set_fs magic for undoing any damange done
by set_fs(KERNEL_DS).  There is no real functional benefit, but this
documents the intent of these calls better, and will allow stubbing the
functions out easily for kernels builds that do not allow address space
overrides in the future.

[hch@lst.de: drop two incorrect hunks, fix a commit log typo]
  Link: http://lkml.kernel.org/r/20200714105505.935079-6-hch@lst.de

Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
Signed-off-by: Andrew Morton &lt;akpm@linux-foundation.org&gt;
Acked-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
Acked-by: Mark Rutland &lt;mark.rutland@arm.com&gt;
Acked-by: Greentime Hu &lt;green.hu@gmail.com&gt;
Acked-by: Geert Uytterhoeven &lt;geert@linux-m68k.org&gt;
Cc: Nick Hu &lt;nickhu@andestech.com&gt;
Cc: Vincent Chen &lt;deanbo422@gmail.com&gt;
Cc: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;
Cc: Palmer Dabbelt &lt;palmer@dabbelt.com&gt;
Link: http://lkml.kernel.org/r/20200710135706.537715-6-hch@lst.de
Signed-off-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: Fix build warning about "PTR_STR" redefinition</title>
<updated>2020-05-30T08:58:30+00:00</updated>
<author>
<name>Thomas Bogendoerfer</name>
<email>tsbogend@alpha.franken.de</email>
</author>
<published>2020-05-30T08:55:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=b3878a6aac1bfc52cf531d2568ae054348b2334a'/>
<id>b3878a6aac1bfc52cf531d2568ae054348b2334a</id>
<content type='text'>
PTR_STR is redefined when CONFIG_TEST_PRINTF is set. This causes the
following build warning:

  CC      lib/test_printf.o
lib/test_printf.c:214:0: warning: "PTR_STR" redefined
 #define PTR_STR "ffff0123456789ab"
 ^
In file included from ./arch/mips/include/asm/dsemul.h:11:0,
                 from ./arch/mips/include/asm/processor.h:22,
                 from ./arch/mips/include/asm/thread_info.h:16,
                 from ./include/linux/thread_info.h:38,
                 from ./include/asm-generic/preempt.h:5,
                 from ./arch/mips/include/generated/asm/preempt.h:1,
                 from ./include/linux/preempt.h:78,
                 from ./include/linux/spinlock.h:51,
                 from ./include/linux/seqlock.h:36,
                 from ./include/linux/time.h:6,
                 from ./include/linux/stat.h:19,
                 from ./include/linux/module.h:13,
                 from lib/test_printf.c:10:
./arch/mips/include/asm/inst.h:20:0: note: this is the location of the previous definition
 #define PTR_STR  ".dword"
 ^

Instead of renaming PTR_STR we move the unaligned macros to a new file,
which is only included inside MIPS code. This way we can safely include
asm.h and can use STR(PTR) again.

Fixes: e701656ec4db ("MIPS: inst.h: Stop including asm.h to avoid various build failures")
Cc: Maciej W. Rozycki" &lt;macro@linux-mips.org&gt;
Reported-by: Tiezhu Yang &lt;yangtiezhu@loongson.cn&gt;
Co-developed-by: Huacai Chen &lt;chenhc@lemote.com&gt;
Signed-off-by: Huacai Chen &lt;chenhc@lemote.com&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
PTR_STR is redefined when CONFIG_TEST_PRINTF is set. This causes the
following build warning:

  CC      lib/test_printf.o
lib/test_printf.c:214:0: warning: "PTR_STR" redefined
 #define PTR_STR "ffff0123456789ab"
 ^
In file included from ./arch/mips/include/asm/dsemul.h:11:0,
                 from ./arch/mips/include/asm/processor.h:22,
                 from ./arch/mips/include/asm/thread_info.h:16,
                 from ./include/linux/thread_info.h:38,
                 from ./include/asm-generic/preempt.h:5,
                 from ./arch/mips/include/generated/asm/preempt.h:1,
                 from ./include/linux/preempt.h:78,
                 from ./include/linux/spinlock.h:51,
                 from ./include/linux/seqlock.h:36,
                 from ./include/linux/time.h:6,
                 from ./include/linux/stat.h:19,
                 from ./include/linux/module.h:13,
                 from lib/test_printf.c:10:
./arch/mips/include/asm/inst.h:20:0: note: this is the location of the previous definition
 #define PTR_STR  ".dword"
 ^

Instead of renaming PTR_STR we move the unaligned macros to a new file,
which is only included inside MIPS code. This way we can safely include
asm.h and can use STR(PTR) again.

Fixes: e701656ec4db ("MIPS: inst.h: Stop including asm.h to avoid various build failures")
Cc: Maciej W. Rozycki" &lt;macro@linux-mips.org&gt;
Reported-by: Tiezhu Yang &lt;yangtiezhu@loongson.cn&gt;
Co-developed-by: Huacai Chen &lt;chenhc@lemote.com&gt;
Signed-off-by: Huacai Chen &lt;chenhc@lemote.com&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: Move unaligned load/store helpers to inst.h</title>
<updated>2020-04-24T16:18:06+00:00</updated>
<author>
<name>Huacai Chen</name>
<email>chenhc@lemote.com</email>
</author>
<published>2020-04-24T10:56:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=d339cd02b888eb8c4508fd772120782eac59a9fa'/>
<id>d339cd02b888eb8c4508fd772120782eac59a9fa</id>
<content type='text'>
Move unaligned load/store helpers from unaligned.c to inst.h, then
other parts of the kernel can use these helpers.

Use __ASSEMBLY__ to guard the definition of "LONG" in asm.h to avoid
build error on IPxx platforms.

Signed-off-by: Huacai Chen &lt;chenhc@lemote.com&gt;
Signed-off-by: Pei Huang &lt;huangpei@loongson.cn&gt;
Reviewed-by: Jiaxun Yang &lt;jiaxun.yang@flygoat.com&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Move unaligned load/store helpers from unaligned.c to inst.h, then
other parts of the kernel can use these helpers.

Use __ASSEMBLY__ to guard the definition of "LONG" in asm.h to avoid
build error on IPxx platforms.

Signed-off-by: Huacai Chen &lt;chenhc@lemote.com&gt;
Signed-off-by: Pei Huang &lt;huangpei@loongson.cn&gt;
Reviewed-by: Jiaxun Yang &lt;jiaxun.yang@flygoat.com&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: make CPU_HAS_LOAD_STORE_LR opt-out</title>
<updated>2020-01-22T18:16:47+00:00</updated>
<author>
<name>Alexander Lobakin</name>
<email>alobakin@dlink.ru</email>
</author>
<published>2020-01-22T10:58:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=18d84e2e55b6abe1e5b8a658ad078796122899fb'/>
<id>18d84e2e55b6abe1e5b8a658ad078796122899fb</id>
<content type='text'>
CPU_HAS_LOAD_STORE_LR was introduced in 932afdeec18b ("MIPS: Add Kconfig
variable for CPUs with unaligned load/store instructions") to make code
in kernel/unaligned.c and lib/mem{cpy,set}.S more intuitive and give a
possibility to easily add new CPUs without these instruction sets in
future.

Hovewer, this variant is not optimal for mainly two reasons:
* For now, we have 20+ CPUs with such instructions and only two (MIPS R6)
  without. It will obviously be more effective and straightforward to
  have an option for these two rather than for the rest.
* You can easily miss the fact that you need to select this option when
  adding a new CPU, while all processors lacking these sets are
  well-known, so the probability of missing something is way much lower.

We can address both points by turning CPU_HAS_LOAD_STORE_LR into opt-out
CPU_NO_LOAD_STORE_LR. This also makes MIPS root Kconfig more clear and
understandable.

Signed-off-by: Alexander Lobakin &lt;alobakin@dlink.ru&gt;
Signed-off-by: Paul Burton &lt;paulburton@kernel.org&gt;
Cc: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Cc: Alexandre Belloni &lt;alexandre.belloni@bootlin.com&gt;
Cc: Microchip Linux Driver Support &lt;UNGLinuxDriver@microchip.com&gt;
Cc: Will Deacon &lt;will@kernel.org&gt;
Cc: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
Cc: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Cc: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;
Cc: Michal Simek &lt;michal.simek@xilinx.com&gt;
Cc: Allison Randal &lt;allison@lohutok.net&gt;
Cc: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: Eric W. Biederman &lt;ebiederm@xmission.com&gt;
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
CPU_HAS_LOAD_STORE_LR was introduced in 932afdeec18b ("MIPS: Add Kconfig
variable for CPUs with unaligned load/store instructions") to make code
in kernel/unaligned.c and lib/mem{cpy,set}.S more intuitive and give a
possibility to easily add new CPUs without these instruction sets in
future.

Hovewer, this variant is not optimal for mainly two reasons:
* For now, we have 20+ CPUs with such instructions and only two (MIPS R6)
  without. It will obviously be more effective and straightforward to
  have an option for these two rather than for the rest.
* You can easily miss the fact that you need to select this option when
  adding a new CPU, while all processors lacking these sets are
  well-known, so the probability of missing something is way much lower.

We can address both points by turning CPU_HAS_LOAD_STORE_LR into opt-out
CPU_NO_LOAD_STORE_LR. This also makes MIPS root Kconfig more clear and
understandable.

Signed-off-by: Alexander Lobakin &lt;alobakin@dlink.ru&gt;
Signed-off-by: Paul Burton &lt;paulburton@kernel.org&gt;
Cc: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Cc: Alexandre Belloni &lt;alexandre.belloni@bootlin.com&gt;
Cc: Microchip Linux Driver Support &lt;UNGLinuxDriver@microchip.com&gt;
Cc: Will Deacon &lt;will@kernel.org&gt;
Cc: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
Cc: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Cc: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;
Cc: Michal Simek &lt;michal.simek@xilinx.com&gt;
Cc: Allison Randal &lt;allison@lohutok.net&gt;
Cc: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: Eric W. Biederman &lt;ebiederm@xmission.com&gt;
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
</pre>
</div>
</content>
</entry>
<entry>
<title>signal: Remove task parameter from force_sig</title>
<updated>2019-05-27T14:36:28+00:00</updated>
<author>
<name>Eric W. Biederman</name>
<email>ebiederm@xmission.com</email>
</author>
<published>2019-05-23T15:17:27+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=3cf5d076fb4d48979f382bc9452765bf8b79e740'/>
<id>3cf5d076fb4d48979f382bc9452765bf8b79e740</id>
<content type='text'>
All of the remaining callers pass current into force_sig so
remove the task parameter to make this obvious and to make
misuse more difficult in the future.

This also makes it clear force_sig passes current into force_sig_info.

Signed-off-by: "Eric W. Biederman" &lt;ebiederm@xmission.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
All of the remaining callers pass current into force_sig so
remove the task parameter to make this obvious and to make
misuse more difficult in the future.

This also makes it clear force_sig passes current into force_sig_info.

Signed-off-by: "Eric W. Biederman" &lt;ebiederm@xmission.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: MemoryMapID (MMID) Support</title>
<updated>2019-02-04T18:56:41+00:00</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@mips.com</email>
</author>
<published>2019-02-02T01:43:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=c8790d657b0a8d42801fb4536f6f106b4b6306e8'/>
<id>c8790d657b0a8d42801fb4536f6f106b4b6306e8</id>
<content type='text'>
Introduce support for using MemoryMapIDs (MMIDs) as an alternative to
Address Space IDs (ASIDs). The major difference between the two is that
MMIDs are global - ie. an MMID uniquely identifies an address space
across all coherent CPUs. In contrast ASIDs are non-global per-CPU IDs,
wherein each address space is allocated a separate ASID for each CPU
upon which it is used. This global namespace allows a new GINVT
instruction be used to globally invalidate TLB entries associated with a
particular MMID across all coherent CPUs in the system, removing the
need for IPIs to invalidate entries with separate ASIDs on each CPU.

The allocation scheme used here is largely borrowed from arm64 (see
arch/arm64/mm/context.c). In essence we maintain a bitmap to track
available MMIDs, and MMIDs in active use at the time of a rollover to a
new MMID version are preserved in the new version. The allocation scheme
requires efficient 64 bit atomics in order to perform reasonably, so
this support depends upon CONFIG_GENERIC_ATOMIC64=n (ie. currently it
will only be included in MIPS64 kernels).

The first, and currently only, available CPU with support for MMIDs is
the MIPS I6500. This CPU supports 16 bit MMIDs, and so for now we cap
our MMIDs to 16 bits wide in order to prevent the bitmap growing to
absurd sizes if any future CPU does implement 32 bit MMIDs as the
architecture manuals suggest is recommended.

When MMIDs are in use we also make use of GINVT instruction which is
available due to the global nature of MMIDs. By executing a sequence of
GINVT &amp; SYNC 0x14 instructions we can avoid the overhead of an IPI to
each remote CPU in many cases. One complication is that GINVT will
invalidate wired entries (in all cases apart from type 0, which targets
the entire TLB). In order to avoid GINVT invalidating any wired TLB
entries we set up, we make sure to create those entries using a reserved
MMID (0) that we never associate with any address space.

Also of note is that KVM will require further work in order to support
MMIDs &amp; GINVT, since KVM is involved in allocating IDs for guests &amp; in
configuring the MMU. That work is not part of this patch, so for now
when MMIDs are in use KVM is disabled.

Signed-off-by: Paul Burton &lt;paul.burton@mips.com&gt;
Cc: linux-mips@vger.kernel.org
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Introduce support for using MemoryMapIDs (MMIDs) as an alternative to
Address Space IDs (ASIDs). The major difference between the two is that
MMIDs are global - ie. an MMID uniquely identifies an address space
across all coherent CPUs. In contrast ASIDs are non-global per-CPU IDs,
wherein each address space is allocated a separate ASID for each CPU
upon which it is used. This global namespace allows a new GINVT
instruction be used to globally invalidate TLB entries associated with a
particular MMID across all coherent CPUs in the system, removing the
need for IPIs to invalidate entries with separate ASIDs on each CPU.

The allocation scheme used here is largely borrowed from arm64 (see
arch/arm64/mm/context.c). In essence we maintain a bitmap to track
available MMIDs, and MMIDs in active use at the time of a rollover to a
new MMID version are preserved in the new version. The allocation scheme
requires efficient 64 bit atomics in order to perform reasonably, so
this support depends upon CONFIG_GENERIC_ATOMIC64=n (ie. currently it
will only be included in MIPS64 kernels).

The first, and currently only, available CPU with support for MMIDs is
the MIPS I6500. This CPU supports 16 bit MMIDs, and so for now we cap
our MMIDs to 16 bits wide in order to prevent the bitmap growing to
absurd sizes if any future CPU does implement 32 bit MMIDs as the
architecture manuals suggest is recommended.

When MMIDs are in use we also make use of GINVT instruction which is
available due to the global nature of MMIDs. By executing a sequence of
GINVT &amp; SYNC 0x14 instructions we can avoid the overhead of an IPI to
each remote CPU in many cases. One complication is that GINVT will
invalidate wired entries (in all cases apart from type 0, which targets
the entire TLB). In order to avoid GINVT invalidating any wired TLB
entries we set up, we make sure to create those entries using a reserved
MMID (0) that we never associate with any address space.

Also of note is that KVM will require further work in order to support
MMIDs &amp; GINVT, since KVM is involved in allocating IDs for guests &amp; in
configuring the MMU. That work is not part of this patch, so for now
when MMIDs are in use KVM is disabled.

Signed-off-by: Paul Burton &lt;paul.burton@mips.com&gt;
Cc: linux-mips@vger.kernel.org
</pre>
</div>
</content>
</entry>
<entry>
<title>mips: kernel: no need to check return value of debugfs_create functions</title>
<updated>2019-01-22T19:17:20+00:00</updated>
<author>
<name>Greg Kroah-Hartman</name>
<email>gregkh@linuxfoundation.org</email>
</author>
<published>2019-01-22T14:57:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=d8140426bc39f7d4f00f6d55e1e7f269a3762ffa'/>
<id>d8140426bc39f7d4f00f6d55e1e7f269a3762ffa</id>
<content type='text'>
When calling debugfs functions, there is no need to ever check the
return value.  The function can work or not, but the code logic should
never do something different based on this.

Cc: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Cc: Paul Burton &lt;paul.burton@mips.com&gt;
Cc: James Hogan &lt;jhogan@kernel.org&gt;
Cc: Yangtao Li &lt;tiny.windzz@gmail.com&gt;
Cc: Andrew Morton &lt;akpm@linux-foundation.org&gt;
Cc: Mike Rapoport &lt;rppt@linux.vnet.ibm.com&gt;
Cc: Mathieu Malaterre &lt;malat@debian.org&gt;
Cc: Huacai Chen &lt;chenhc@lemote.com&gt;
Cc: Marcin Nowakowski &lt;marcin.nowakowski@mips.com&gt;
Cc: Yasha Cherikovsky &lt;yasha.che3@gmail.com&gt;
Cc: linux-mips@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
Signed-off-by: Paul Burton &lt;paul.burton@mips.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
When calling debugfs functions, there is no need to ever check the
return value.  The function can work or not, but the code logic should
never do something different based on this.

Cc: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Cc: Paul Burton &lt;paul.burton@mips.com&gt;
Cc: James Hogan &lt;jhogan@kernel.org&gt;
Cc: Yangtao Li &lt;tiny.windzz@gmail.com&gt;
Cc: Andrew Morton &lt;akpm@linux-foundation.org&gt;
Cc: Mike Rapoport &lt;rppt@linux.vnet.ibm.com&gt;
Cc: Mathieu Malaterre &lt;malat@debian.org&gt;
Cc: Huacai Chen &lt;chenhc@lemote.com&gt;
Cc: Marcin Nowakowski &lt;marcin.nowakowski@mips.com&gt;
Cc: Yasha Cherikovsky &lt;yasha.che3@gmail.com&gt;
Cc: linux-mips@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
Signed-off-by: Paul Burton &lt;paul.burton@mips.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Remove 'type' argument from access_ok() function</title>
<updated>2019-01-04T02:57:57+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2019-01-04T02:57:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=96d4f267e40f9509e8a66e2b39e8b95655617693'/>
<id>96d4f267e40f9509e8a66e2b39e8b95655617693</id>
<content type='text'>
Nobody has actually used the type (VERIFY_READ vs VERIFY_WRITE) argument
of the user address range verification function since we got rid of the
old racy i386-only code to walk page tables by hand.

It existed because the original 80386 would not honor the write protect
bit when in kernel mode, so you had to do COW by hand before doing any
user access.  But we haven't supported that in a long time, and these
days the 'type' argument is a purely historical artifact.

A discussion about extending 'user_access_begin()' to do the range
checking resulted this patch, because there is no way we're going to
move the old VERIFY_xyz interface to that model.  And it's best done at
the end of the merge window when I've done most of my merges, so let's
just get this done once and for all.

This patch was mostly done with a sed-script, with manual fix-ups for
the cases that weren't of the trivial 'access_ok(VERIFY_xyz' form.

There were a couple of notable cases:

 - csky still had the old "verify_area()" name as an alias.

 - the iter_iov code had magical hardcoded knowledge of the actual
   values of VERIFY_{READ,WRITE} (not that they mattered, since nothing
   really used it)

 - microblaze used the type argument for a debug printout

but other than those oddities this should be a total no-op patch.

I tried to fix up all architectures, did fairly extensive grepping for
access_ok() uses, and the changes are trivial, but I may have missed
something.  Any missed conversion should be trivially fixable, though.

Signed-off-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Nobody has actually used the type (VERIFY_READ vs VERIFY_WRITE) argument
of the user address range verification function since we got rid of the
old racy i386-only code to walk page tables by hand.

It existed because the original 80386 would not honor the write protect
bit when in kernel mode, so you had to do COW by hand before doing any
user access.  But we haven't supported that in a long time, and these
days the 'type' argument is a purely historical artifact.

A discussion about extending 'user_access_begin()' to do the range
checking resulted this patch, because there is no way we're going to
move the old VERIFY_xyz interface to that model.  And it's best done at
the end of the merge window when I've done most of my merges, so let's
just get this done once and for all.

This patch was mostly done with a sed-script, with manual fix-ups for
the cases that weren't of the trivial 'access_ok(VERIFY_xyz' form.

There were a couple of notable cases:

 - csky still had the old "verify_area()" name as an alias.

 - the iter_iov code had magical hardcoded knowledge of the actual
   values of VERIFY_{READ,WRITE} (not that they mattered, since nothing
   really used it)

 - microblaze used the type argument for a debug printout

but other than those oddities this should be a total no-op patch.

I tried to fix up all architectures, did fairly extensive grepping for
access_ok() uses, and the changes are trivial, but I may have missed
something.  Any missed conversion should be trivially fixable, though.

Signed-off-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: Fix do_ade() closing brace indentation</title>
<updated>2018-11-10T01:20:01+00:00</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@mips.com</email>
</author>
<published>2018-11-09T20:07:55+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=c7adfaea4bf445b4715ffb031fcd9313b4cf63d5'/>
<id>c7adfaea4bf445b4715ffb031fcd9313b4cf63d5</id>
<content type='text'>
A closing brace in do_ade() has misleading indentation; fix it.

Signed-off-by: Paul Burton &lt;paul.burton@mips.com&gt;
Patchwork: https://patchwork.linux-mips.org/patch/21066/
Cc: linux-mips@linux-mips.org
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
A closing brace in do_ade() has misleading indentation; fix it.

Signed-off-by: Paul Burton &lt;paul.burton@mips.com&gt;
Patchwork: https://patchwork.linux-mips.org/patch/21066/
Cc: linux-mips@linux-mips.org
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: unaligned: Remove FP &amp; MSA code when unsupported</title>
<updated>2018-11-09T18:23:17+00:00</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@mips.com</email>
</author>
<published>2018-11-07T23:14:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=85164fd8b053200cfc811d7a77afeb507968226c'/>
<id>85164fd8b053200cfc811d7a77afeb507968226c</id>
<content type='text'>
When CONFIG_MIPS_FP_SUPPORT=n we don't support floating point, so remove
support for floating point instructions from emulate_load_store_insn() &amp;
emulate_load_store_microMIPS(). This code should not be needed &amp; relies
upon access to FPU state in struct task_struct which will later be
removed.

Similarly &amp; for the same reasons, when CONFIG_CPU_HAS_MSA=n remove
support for MSA instructions. Since MSA support depends upon FP support
this is implied when CONFIG_MIPS_FP_SUPPORT=n.

Signed-off-by: Paul Burton &lt;paul.burton@mips.com&gt;
Patchwork: https://patchwork.linux-mips.org/patch/21020/
Cc: linux-mips@linux-mips.org
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
When CONFIG_MIPS_FP_SUPPORT=n we don't support floating point, so remove
support for floating point instructions from emulate_load_store_insn() &amp;
emulate_load_store_microMIPS(). This code should not be needed &amp; relies
upon access to FPU state in struct task_struct which will later be
removed.

Similarly &amp; for the same reasons, when CONFIG_CPU_HAS_MSA=n remove
support for MSA instructions. Since MSA support depends upon FP support
this is implied when CONFIG_MIPS_FP_SUPPORT=n.

Signed-off-by: Paul Burton &lt;paul.burton@mips.com&gt;
Patchwork: https://patchwork.linux-mips.org/patch/21020/
Cc: linux-mips@linux-mips.org
</pre>
</div>
</content>
</entry>
</feed>
