linux-toradex.git/arch/mips/kernel, branch v4.2-rc5

MIPS: asm-offset.c: Patch up various comments refering to the old filename.

2015-07-14T14:05:49+00:00

arch/mips/tools/offset.c was renamed to arch/mips/kernel/asm-offsets.c
for v2.6.14.

Signed-off-by: Ralf Baechle

MIPS: O32: Use compat_sys_getsockopt.

2015-07-10T09:02:22+00:00

We were using the native syscall and that results in subtle breakage.

This is the same issue as fixed in 077d0e65618f27b2199d622e12ada6d8f3dbd862
(MIPS: N32: Use compat getsockopt syscall) but that commit did fix it only
for N32.

Signed-off-by: Ralf Baechle 
Link: https://bugzilla.kernel.org/show_bug.cgi?id=100291

MIPS: c-r4k: Fix cache flushing for MT cores

2015-07-10T08:59:16+00:00

MT_SMP is not the only SMP option for MT cores. The MT_SMP option
allows more than one VPE per core to appear as a secondary CPU in the
system. Because of how CM works, it propagates the address-based
cache ops to the secondary cores but not the index-based ones.
Because of that, the code does not use IPIs to flush the L1 caches on
secondary cores because the CM would have done that already. However,
the CM functionality is independent of the type of SMP kernel so even in
non-MT kernels, IPIs are not necessary. As a result of which, we change
the conditional to depend on the CM presence. Moreover, since VPEs on
the same core share the same L1 caches, there is no need to send an
IPI on all of them so we calculate a suitable cpumask with only one
VPE per core.

Signed-off-by: Markos Chandras 
Cc:  # 3.15+
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10654/
Signed-off-by: Ralf Baechle

MIPS: cps-vec: Use macros for various arithmetics and memory operations

2015-07-09T09:17:01+00:00

Replace lw/sw and various arithmetic instructions with macros so the
code can work on 64-bit kernels as well.

Cc:  # 3.16+
Reviewed-by: Paul Burton 
Signed-off-by: Markos Chandras 
Cc: linux-mips@linux-mips.org
Cc: stable@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10591/
Signed-off-by: Ralf Baechle

MIPS: kernel: cps-vec: Replace KSEG0 with CKSEG0

2015-07-09T09:15:44+00:00

In preparation for 64-bit CPS support, we replace KSEG0 with CKSEG0
so 64-bit kernels can be supported.

Cc:  # 3.16+
Reviewed-by: Paul Burton 
Signed-off-by: Markos Chandras 
Cc: linux-mips@linux-mips.org
Cc: stable@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10590/
Signed-off-by: Ralf Baechle

MIPS: kernel: cps-vec: Use ta0-ta3 pseudo-registers for 64-bit

2015-07-09T09:15:17+00:00

The cps-vec code assumes O32 ABI and uses t4-t7 in quite a few places. This
breaks the build on 64-bit. As a result of which, use the pseudo-registers
ta0-ta3 to make the code compatible with 64-bit.

Cc:  # 3.16+
Reviewed-by: Paul Burton 
Signed-off-by: Markos Chandras 
Cc: linux-mips@linux-mips.org
Cc: stable@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10589/
Signed-off-by: Ralf Baechle

MIPS: kernel: cps-vec: Replace mips32r2 ISA level with mips64r2

2015-07-09T09:14:48+00:00

mips32r2 is a subset of mips64r2, so we replace mips32r2 with mips64r2
in preparation for 64-bit CPS support.

Cc:  # 3.16+
Reviewed-by: Paul Burton 
Signed-off-by: Markos Chandras 
Cc: linux-mips@linux-mips.org
Cc: stable@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10588/
Signed-off-by: Ralf Baechle

MIPS: kernel: cps-vec: Replace 'la' macro with PTR_LA

2015-07-09T09:13:33+00:00

The PTR_LA macro will pick the correct "la" or "dla" macro to
load an address to a register. This gets rids of the following
warnings (and others) when building a 64-bit CPS kernel:

arch/mips/kernel/cps-vec.S:63: Warning: la used to load 64-bit address
arch/mips/kernel/cps-vec.S:159: Warning: la used to load 64-bit address
arch/mips/kernel/cps-vec.S:220: Warning: la used to load 64-bit address
arch/mips/kernel/cps-vec.S:240: Warning: la used to load 64-bit address
[...]

Cc:  # 3.16+
Reviewed-by: Paul Burton 
Signed-off-by: Markos Chandras 
Cc: linux-mips@linux-mips.org
Cc: stable@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10587/
Signed-off-by: Ralf Baechle

MIPS: kernel: smp-cps: Fix 64-bit compatibility errors due to pointer casting

2015-07-09T09:12:57+00:00

Commit 1d8f1f5a780a ("MIPS: smp-cps: hotplug support") added hotplug
support in the SMP/CPS implementation but it introduced a few build problems
on 64-bit kernels due to pointer being casted to and from 'int' C types. We
fix this problem by using 'unsigned long' instead which should match the size
of the pointers in 32/64-bit kernels. Finally, we fix the comment since the
CM base address is loaded to v1($3) instead of v0.

Fixes the following build problems:

arch/mips/kernel/smp-cps.c: In function 'wait_for_sibling_halt':
arch/mips/kernel/smp-cps.c:366:17: error: cast from pointer to integer of
different size [-Werror=pointer-to-int-cast]
[...]
arch/mips/kernel/smp-cps.c: In function 'cps_cpu_die':
arch/mips/kernel/smp-cps.c:427:13: error: cast to pointer
from integer of different size [-Werror=int-to-pointer-cast]

cc1: all warnings being treated as errors

Fixes: 1d8f1f5a780a ("MIPS: smp-cps: hotplug support")
Cc:  # 3.16+
Reviewed-by: Paul Burton 
Signed-off-by: Markos Chandras 
Cc: linux-mips@linux-mips.org
Cc: stable@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10586/
Signed-off-by: Ralf Baechle

MIPS: Fix branch emulation for BLTC and BGEC instructions

2015-07-09T09:10:40+00:00

Commits f1b44067c19258b7614e3cd09dfe8d8e12ff5895 ("MIPS: Emulate the
new MIPS R6 B{L,G}T{Z,}{AL,}C instructions") and commit
a8ff66f52d3f17b5ae793955270675c197f73d6c ("MIPS: Emulate the new MIPS
R6 B{L,G}E{Z,}{AL,}C instructions") added support for emulating various
branch compact instructions. However, it missed the case for those which
use the old BLEZL and BGTZL opcodes leading to random crashes when the R6
emulator is disabled. We fix this by ensuring that the 'rt' field is not
zero which is always true for these branch compact instructions.

Fixes: f1b44067c192 ("MIPS: Emulate the new MIPS R6 B{L,G}T{Z,}{AL,}C instructions")
Fixes: a8ff66f52d3f ("MIPS: Emulate the new MIPS R6 B{L,G}E{Z,}{AL,}C instructions")
Cc:  # 4.0+
Signed-off-by: Markos Chandras 
Cc: linux-mips@linux-mips.org
Cc: Markos Chandras 
Patchwork: https://patchwork.linux-mips.org/patch/10582/
Signed-off-by: Ralf Baechle