linux-toradex.git/arch/mips/loongson32/Platform, branch master Linux kernel for Apalis and Colibri modules MIPS: loongson32: Switch to generic core 2025-08-29T20:34:31+00:00 Keguang Zhang keguang.zhang@gmail.com 2025-07-16T11:25:16+00:00 85c4354076ca2f84f6473073005174905880e998 The generic MIPS core is fully compatible with Loongson-1 SoCs, so migrate Loongson-1 to it. Main changes are: - Merge CPU_LOONGSON1B and CPU_LOONGSON1C into a unified CPU_LOONGSON32, as both are based on the GS232 core. - Consolidate LOONGSON1_LS1B and LOONGSON1_LS1C Kconfig options into MACH_LOONGSON32. - Enable MACH_GENERIC_CORE and remove the legacy custom implementation. - Remove all Loongson-1 platform devices and associated code, which are now obsolete due to Device Tree support. - Misc cleanup. Partially based on earlier work by Jiaxun Yang. Link: https://lore.kernel.org/all/20190411121915.8040-4-jiaxun.yang@flygoat.com/ Signed-off-by: Keguang Zhang <keguang.zhang@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> 
The generic MIPS core is fully compatible with Loongson-1 SoCs,
so migrate Loongson-1 to it.

Main changes are:
 - Merge CPU_LOONGSON1B and CPU_LOONGSON1C into a unified CPU_LOONGSON32,
   as both are based on the GS232 core.
 - Consolidate LOONGSON1_LS1B and LOONGSON1_LS1C Kconfig options into
   MACH_LOONGSON32.
 - Enable MACH_GENERIC_CORE and remove the legacy custom implementation.
 - Remove all Loongson-1 platform devices and associated code,
   which are now obsolete due to Device Tree support.
 - Misc cleanup.

Partially based on earlier work by Jiaxun Yang.

Link: https://lore.kernel.org/all/20190411121915.8040-4-jiaxun.yang@flygoat.com/
Signed-off-by: Keguang Zhang <keguang.zhang@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
MIPS: Only include the platform file needed 2020-05-12T22:17:18+00:00 Thomas Bogendoerfer tsbogend@alpha.franken.de 2020-05-06T16:24:02+00:00 26bff9eb49201aeb4e1b32d698c191831a39f5d4 Instead of including all Platform files, we simply include the needed one and avoid clashes with makefile variables. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> 
Instead of including all Platform files, we simply include the
needed one and avoid clashes with makefile variables.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
MIPS: Loongson: Rename LOONGSON1 to LOONGSON32 2019-11-11T18:43:13+00:00 Huacai Chen chenhc@lemote.com 2019-11-04T06:11:20+00:00 b2afb64cccd243afd8a4337d8ee4c2f2afbe991d Now old Loongson-2E/2F use LOONGSON2EF and will be removed in future, newer Loongson-2/3 use LOONGSON64. So rename LOONGSON1 to LOONGSON32 will make the naming style more unified. Signed-off-by: Huacai Chen <chenhc@lemote.com> [paulburton@kernel.org: Fix checkpatch whitespace warning in irqflags.h] Signed-off-by: Paul Burton <paulburton@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Cc: linux-mips@vger.kernel.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: Huacai Chen <chenhuacai@gmail.com> 
Now old Loongson-2E/2F use LOONGSON2EF and will be removed in future,
newer Loongson-2/3 use LOONGSON64. So rename LOONGSON1 to LOONGSON32
will make the naming style more unified.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
[paulburton@kernel.org: Fix checkpatch whitespace warning in irqflags.h]
Signed-off-by: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@linux-mips.org
Cc: linux-mips@vger.kernel.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: Huacai Chen <chenhuacai@gmail.com>
MIPS: Loongson32: Revert ISA level to MIPS32R2 2019-01-23T01:32:23+00:00 Jiaxun Yang jiaxun.yang@flygoat.com 2019-01-22T13:04:12+00:00 7e280f6b0549f3c3e9e94206954d49f87c2048d0 GS232 core have implemented all necessary mips32r2 instructions. Serval missing FP instructions can be emulated by kernel. The issue of di instruction have been solved. Thus we revert the ISA level back to MIPS32R2. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org Cc: keguang.zhang@gmail.com 
GS232 core have implemented all necessary mips32r2 instructions.
Serval missing FP instructions can be emulated by kernel.

The issue of di instruction have been solved.
Thus we revert the ISA level back to MIPS32R2.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Cc: keguang.zhang@gmail.com
MIPS: Loongson32: Set load address to 0x80200000 2019-01-22T19:18:52+00:00 Jiaxun Yang jiaxun.yang@flygoat.com 2019-01-22T13:04:14+00:00 d1b83f0f631ba58e444773a554648f9006d911e8 PMON bootloader on Loongson-1C will use memory between 0x80100000 and 0x80200000 as stack. Use 0x80100000 as load address may hang the bootloader during loading. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org Cc: keguang.zhang@gmail.com 
PMON bootloader on Loongson-1C will use memory between
0x80100000 and 0x80200000 as stack.

Use 0x80100000 as load address may hang the bootloader
during loading.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Cc: keguang.zhang@gmail.com
MIPS: Loongson: Merge load addresses 2018-07-31T01:59:01+00:00 谢致邦 (XIE Zhibang) Yeking@Red54.com 2017-01-04T13:30:58+00:00 60bc84e227d24fdb1ac2211c574a88ecd7c836a0 Systems based upon the Loongson 1B & 1C CPUs share the same load address, as do those based upon Loongson 1A. Unify the definition of this load address to reduce duplication & avoid the need for an extra Loongson 1A case in future. [paul.burton@mips.com: Rewrite commit message.] Signed-off-by: 谢致邦 (XIE Zhibang) <Yeking@Red54.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/14927/ Cc: linux-mips@linux-mips.org 
Systems based upon the Loongson 1B & 1C CPUs share the same load
address, as do those based upon Loongson 1A. Unify the definition of
this load address to reduce duplication & avoid the need for an extra
Loongson 1A case in future.

[paul.burton@mips.com: Rewrite commit message.]

Signed-off-by: 谢致邦 (XIE Zhibang) <Yeking@Red54.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/14927/
Cc: linux-mips@linux-mips.org
MIPS: Loongson: Set Loongson32 to MIPS32R1 2018-07-31T01:54:15+00:00 谢致邦 (XIE Zhibang) Yeking@Red54.com 2017-06-01T10:41:34+00:00 968dc5a0eaca707f8eb2fbad57d9fbbf3284541e LS232 (Loonson 2-issue 32-bit, also called GS232 (Godson 2-issue 32-bit)) is the CPU core (microarchitecture) of Loongson 1A/1B/1C. According to "LS232 用户手册 (LS232 User Manual)", LS232 implements the MIPS32 Release 1 instruction set, and part of the MIPS32 Release 2 instruction set. In the manual, LS232 implements all of the MIPS32R2 instruction set except the FPU instructions, and LS232 also implements 5 FPU instructions of the MIPS32R2 instruction set: CEIL.L.fmt, CVT.L.fmt, FLOOR.L.fmt, TRUNC.L.fmt, and ROUND.L.fmt. But a bug of the DI instruction has been found during tests, the DI instruction can not disable interrupts in arch_local_irq_disable() with CONFIG_PREEMPT_NONE=y and CFLAGS='-mno-branch-likely' in some cases. [paul.burton@mips.com: - Remove the _MIPS_ISA redefinition to match the change made for the generic MIPSr1 CPUs by commit 344ebf09949c ("MIPS: Always use -march=<arch>, not -<arch> shortcuts").] Signed-off-by: 谢致邦 (XIE Zhibang) <Yeking@Red54.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/16155/ Cc: linux-mips@linux-mips.org Cc: ralf@linux-mips.org 
LS232 (Loonson 2-issue 32-bit, also called GS232 (Godson 2-issue 32-bit))
is the CPU core (microarchitecture) of Loongson 1A/1B/1C.

According to "LS232 用户手册 (LS232 User Manual)", LS232 implements the
MIPS32 Release 1 instruction set, and part of the MIPS32 Release 2
instruction set.

In the manual, LS232 implements all of the MIPS32R2 instruction set
except the FPU instructions, and LS232 also implements 5 FPU
instructions of the MIPS32R2 instruction set: CEIL.L.fmt, CVT.L.fmt,
FLOOR.L.fmt, TRUNC.L.fmt, and ROUND.L.fmt.

But a bug of the DI instruction has been found during tests, the DI
instruction can not disable interrupts in arch_local_irq_disable() with
CONFIG_PREEMPT_NONE=y and CFLAGS='-mno-branch-likely' in some cases.

[paul.burton@mips.com:
  - Remove the _MIPS_ISA redefinition to match the change made for the
    generic MIPSr1 CPUs by commit 344ebf09949c ("MIPS: Always use
    -march=<arch>, not -<arch> shortcuts").]

Signed-off-by: 谢致邦 (XIE Zhibang) <Yeking@Red54.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/16155/
Cc: linux-mips@linux-mips.org
Cc: ralf@linux-mips.org
MIPS: Loongson1C: Add board support 2016-10-04T14:13:57+00:00 Yang Ling gnaygnil@gmail.com 2016-05-19T04:29:30+00:00 12e3280b33fe1ada85b84f67613d03e1b6d8dbf6 Adds basic platform devices for Loongson1C, including serial port and ethernet. Signed-off-by: Yang Ling <gnaygnil@gmail.com> Cc: keguang.zhang@gmail.com Cc: chenhc@lemote.com Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13304/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Adds basic platform devices for Loongson1C, including serial port
and ethernet.

Signed-off-by: Yang Ling <gnaygnil@gmail.com>
Cc: keguang.zhang@gmail.com
Cc: chenhc@lemote.com
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13304/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
MIPS: Loongson: Naming style cleanup and rework 2015-06-21T19:53:59+00:00 Huacai Chen chenhc@lemote.com 2015-04-21T02:00:35+00:00 30ad29bb48881ee11f5daf30c6fc50292ae08c57 Currently, code of Loongson-2/3 is under loongson directory and code of Loongson-1 is under loongson1 directory. Besides, there are Kconfig options such as MACH_LOONGSON and MACH_LOONGSON1. This naming style is very ugly and confusing. Since Loongson-2/3 are both 64-bit general- purpose CPU while Loongson-1 is 32-bit SoC, we rename both file names and Kconfig symbols from loongson/loongson1 to loongson64/loongson32. [ralf@linux-mips.org: Resolve a number of simple conflicts.] Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: Kelvin Cheung <keguang.zhang@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/9790/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Currently, code of Loongson-2/3 is under loongson directory and code of
Loongson-1 is under loongson1 directory. Besides, there are Kconfig
options such as MACH_LOONGSON and MACH_LOONGSON1. This naming style is
very ugly and confusing. Since Loongson-2/3 are both 64-bit general-
purpose CPU while Loongson-1 is 32-bit SoC, we rename both file names
and Kconfig symbols from loongson/loongson1 to loongson64/loongson32.

[ralf@linux-mips.org: Resolve a number of simple conflicts.]

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: Kelvin Cheung <keguang.zhang@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/9790/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>