linux-toradex.git/arch/mips/loongson64, branch master

MIPS: loongson64: add IRQ work based on self-IPI

2026-06-29T09:36:36+00:00

Since the commit 91840be8f710 ("irq_work: Fix use-after-free in
irq_work_single() on PREEMPT_RT"), we observed the performance of
execve() is significantly impacted on MIPS.

While we are unsure how that commit caused the impact or how to improve
it (or even if it can be improved at all), implementing IRQ work with
self-IPI seems able to mitigate the impaction.

Perhaps this can/should be implemented for other MIPS architecture
processors as well, but we don't have the enough knowledge of them, nor
access to the hardware.  So only implement it for loongson64 here.

Link: https://lore.kernel.org/6be1cdd5f91dd7418a32ff372a6f3ae259b19195.camel@xry111.site/
Signed-off-by: Xi Ruoyao 
Reviewed-by: Huacai Chen 
Reviewed-by: Sebastian Andrzej Siewior 
Signed-off-by: Thomas Bogendoerfer

Merge tag 'irq-drivers-2026-04-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

2026-04-14T17:18:10+00:00

Pull interrupt chip driver updates from Thomas Gleixner:

 - A large refactoring for the Renesas RZV2H driver to add new interrupt
   types cleanly

 - A large refactoring for the Renesas RZG2L driver to add support the
   new RZ/G3L variant

 - Add support for the new NXP S32N79 chip in the IMX irq-steer driver

 - Add support for the Apple AICv3 variant

 - Enhance the Loongson PCH LPC driver so it can be used on MIPS with
   device tree firmware

 - Allow the PIC32 EVIC driver to be built independent of MIPS in
   compile tests

 - The usual small fixes and enhancements all over the place

* tag 'irq-drivers-2026-04-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (46 commits)
  irqchip/irq-pic32-evic: Add __maybe_unused for board_bind_eic_interrupt in COMPILE_TEST
  irqchip/renesas-rzv2h: Kill icu_err string
  irqchip/renesas-rzv2h: Kill swint_names[]
  irqchip/renesas-rzv2h: Kill swint_idx[]
  irqchip/renesas-rzg2l: Add NMI support
  irqchip/renesas-rzg2l: Clear the shared interrupt bit in rzg2l_irqc_free()
  irqchip/renesas-rzg2l: Replace raw_spin_{lock,unlock} with guard() in rzg2l_irq_set_type()
  irqchip/gic-v3: Print a warning for out-of-range interrupt numbers
  irqchip/renesas-rzg2l: Add shared interrupt support
  irqchip/renesas-rzg2l: Add RZ/G3L support
  irqchip/renesas-rzg2l: Drop IRQC_IRQ_COUNT macro
  irqchip/renesas-rzg2l: Drop IRQC_TINT_START macro
  irqchip/renesas-rzg2l: Drop IRQC_NUM_IRQ macro
  irqchip/renesas-rzg2l: Dynamically allocate fwspec array
  irqchip/renesas-rzg2l: Split rzfive_irqc_{mask,unmask} into separate IRQ and TINT handlers
  irqchip/renesas-rzg2l: Split rzfive_tint_irq_endisable() into separate IRQ and TINT helpers
  irqchip/renesas-rzg2l: Replace rzg2l_irqc_irq_{enable,disable} with TINT-specific handlers
  irqchip/renesas-rzg2l: Split set_type handler into separate IRQ and TINT functions
  irqchip/renesas-rzg2l: Split EOI handler into separate IRQ and TINT functions
  irqchip/renesas-rzg2l: Replace single irq_chip with per-region irq_chip instances
  ...

MIPS: Loongson64: env: Check UARTs passed by LEFI cautiously

2026-04-01T19:49:44+00:00

Some firmware does not set nr_uarts properly and passes empty items.
Iterate at most min(system->nr_uarts, MAX_UARTS) items to prevent
out-of-bounds access, and ignore UARTs with addr 0 silently.

Meanwhile, our DT only works with UPIO_MEM but theoretically firmware
may pass other IO types, so explicitly check against that.

Tested on Loongson-LS3A4000-7A1000-NUC-SE.

Fixes: 3989ed418483 ("MIPS: Loongson64: env: Fixup serial clock-frequency when using LEFI")
Cc: stable@vger.kernel.org
Reviewed-by: Yao Zi 
Signed-off-by: Rong Zhang 
Reviewed-by: Jiaxun Yang 
Signed-off-by: Thomas Bogendoerfer

MIPS: loongson64: Override arch_dynirq_lower_bound to reserve LPC IRQs

2026-03-26T15:15:02+00:00

On some Loongson 3A devices, a LPC bus is present and some legacy devices
(e.g. 8259) on it expect hardcoded low interrupt numbers. However currently
the expected low range interrupt numbers are not exempted from the dynamic
allocation, which leads to conflicts when registering LPC interrupts in the
fixed range.

Override arch_dynirq_lower_bound() to reserve these low range interrupt
numbers and prevent them from being dynamically allocated.

Signed-off-by: Icenowy Zheng 
Signed-off-by: Thomas Gleixner 
Reviewed-by: Huacai Chen 
Link: https://patch.msgid.link/20260321092032.3502701-2-zhengxingda@iscas.ac.cn

treewide: Replace kmalloc with kmalloc_obj for non-scalar types

2026-02-21T09:02:28+00:00

This is the result of running the Coccinelle script from
scripts/coccinelle/api/kmalloc_objs.cocci. The script is designed to
avoid scalar types (which need careful case-by-case checking), and
instead replace kmalloc-family calls that allocate struct or union
object instances:

Single allocations:	kmalloc(sizeof(TYPE), ...)
are replaced with:	kmalloc_obj(TYPE, ...)

Array allocations:	kmalloc_array(COUNT, sizeof(TYPE), ...)
are replaced with:	kmalloc_objs(TYPE, COUNT, ...)

Flex array allocations:	kmalloc(struct_size(PTR, FAM, COUNT), ...)
are replaced with:	kmalloc_flex(*PTR, FAM, COUNT, ...)

(where TYPE may also be *VAR)

The resulting allocations no longer return "void *", instead returning
"TYPE *".

Signed-off-by: Kees Cook

Merge tag 'mips_7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

2026-02-16T17:30:44+00:00

Pull MIPS updates from Thomas Bogendoerfer:
 "Cleanups and fixes"

* tag 'mips_7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (28 commits)
  Revert "clk: microchip: core: allow driver to be compiled with COMPILE_TEST"
  Revert "clk: microchip: fix typo in reference to a config option"
  MIPS: Implement ARCH_HAS_CC_CAN_LINK
  MIPS: rb532: Fix MMIO UART resource registration
  MIPS: Work around LLVM bug when gp is used as global register variable
  MIPS: Loongson64: env: Fixup serial clock-frequency when using LEFI
  MIPS: Loongson2ef: Use pcibios_align_resource() to block io range
  MIPS: Loongson2ef: Register PCI controller in early stage
  clk: microchip: fix typo in reference to a config option
  MIPS: Loongson64: dts: fix phy-related definition of LS7A GMAC
  clk: microchip: core: allow driver to be compiled with COMPILE_TEST
  MIPS: drop unused pic32.h header
  watchdog: pic32-wdt: update include to use pic32.h from platform_data
  watchdog: pic32-dmt: update include to use pic32.h from platform_data
  serial: pic32_uart: update include to use pic32.h from platform_data
  rtc: pic32: update include to use pic32.h from platform_data
  pinctrl: pic32: update include to use pic32.h from platform_data
  mmc: sdhci-pic32: update include to use pic32.h from platform_data
  irqchip/irq-pic32-evic: update include to use pic32.h from platform_data
  clk: microchip: core: update include to use pic32.h from platform_data
  ...

MIPS: Loongson64: env: Fixup serial clock-frequency when using LEFI

2026-02-05T09:01:19+00:00

When booting from LEFI firmware, the devicetree is chosen by matching
bridge type and CPU PRID. However, serials on Loongson devices may not
have the same clock frequency across different boards. For example,
CPU UARTs found on Loongson 3A4000 is supplied by the system clock,
which may be either 25MHz or 100MHz.

Luckily, LEFI firmware interface provides information about UART
address and corresponding clock frequency. Let's fixup clock-frequency
properties for serials after FDT selection by matching FDT nodes with
addresses provided by firmware.

Signed-off-by: Yao Zi 
Reviewed-by: Jiaxun Yang 
Signed-off-by: Thomas Bogendoerfer

mips: drop paging_init()

2026-01-27T04:02:19+00:00

All three variants of paging_init() on MIPS are wrappers for
pagetable_init().

Instead of having three identical wrappers, call pagetable_init() directly
from setup_arch() and remove the unnecessary paging_init() functions.

Link: https://lkml.kernel.org/r/20260111082105.290734-26-rppt@kernel.org
Signed-off-by: Mike Rapoport (Microsoft) 
Cc: Alexander Gordeev 
Cc: Alex Shi 
Cc: Andreas Larsson 
Cc: "Borislav Petkov (AMD)" 
Cc: Catalin Marinas 
Cc: David Hildenbrand 
Cc: David S. Miller 
Cc: Dinh Nguyen 
Cc: Geert Uytterhoeven 
Cc: Guo Ren 
Cc: Heiko Carstens 
Cc: Helge Deller 
Cc: Huacai Chen 
Cc: Ingo Molnar 
Cc: Johannes Berg 
Cc: John Paul Adrian Glaubitz 
Cc: Jonathan Corbet 
Cc: Klara Modin 
Cc: Liam Howlett 
Cc: Lorenzo Stoakes 
Cc: Magnus Lindholm 
Cc: Matt Turner 
Cc: Max Filippov 
Cc: Michael Ellerman 
Cc: Michal Hocko 
Cc: Michal Simek 
Cc: Muchun Song 
Cc: Oscar Salvador 
Cc: Palmer Dabbelt 
Cc: Pratyush Yadav 
Cc: Richard Weinberger 
Cc: "Ritesh Harjani (IBM)" 
Cc: Russell King 
Cc: Stafford Horne 
Cc: Suren Baghdasaryan 
Cc: Thomas Bogendoerfer 
Cc: Thomas Gleixner 
Cc: Vasily Gorbik 
Cc: Vineet Gupta 
Cc: Vlastimil Babka 
Cc: Will Deacon 
Signed-off-by: Andrew Morton

arch, mm: consolidate initialization of nodes, zones and memory map

2026-01-27T04:02:18+00:00

To initialize node, zone and memory map data structures every architecture
calls free_area_init() during setup_arch() and passes it an array of zone
limits.

Beside code duplication it creates "interesting" ordering cases between
allocation and initialization of hugetlb and the memory map.  Some
architectures allocate hugetlb pages very early in setup_arch() in certain
cases, some only create hugetlb CMA areas in setup_arch() and sometimes
hugetlb allocations happen mm_core_init().

With arch_zone_limits_init() helper available now on all architectures it
is no longer necessary to call free_area_init() from architecture setup
code.  Rather core MM initialization can call arch_zone_limits_init() in a
single place.

This allows to unify ordering of hugetlb vs memory map allocation and
initialization.

Remove the call to free_area_init() from architecture specific code and
place it in a new mm_core_init_early() function that is called immediately
after setup_arch().

After this refactoring it is possible to consolidate hugetlb allocations
and eliminate differences in ordering of hugetlb and memory map
initialization among different architectures.

As the first step of this consolidation move hugetlb_bootmem_alloc() to
mm_core_early_init().

Link: https://lkml.kernel.org/r/20260111082105.290734-24-rppt@kernel.org
Signed-off-by: Mike Rapoport (Microsoft) 
Cc: Alexander Gordeev 
Cc: Alex Shi 
Cc: Andreas Larsson 
Cc: "Borislav Petkov (AMD)" 
Cc: Catalin Marinas 
Cc: David Hildenbrand 
Cc: David S. Miller 
Cc: Dinh Nguyen 
Cc: Geert Uytterhoeven 
Cc: Guo Ren 
Cc: Heiko Carstens 
Cc: Helge Deller 
Cc: Huacai Chen 
Cc: Ingo Molnar 
Cc: Johannes Berg 
Cc: John Paul Adrian Glaubitz 
Cc: Jonathan Corbet 
Cc: Klara Modin 
Cc: Liam Howlett 
Cc: Lorenzo Stoakes 
Cc: Magnus Lindholm 
Cc: Matt Turner 
Cc: Max Filippov 
Cc: Michael Ellerman 
Cc: Michal Hocko 
Cc: Michal Simek 
Cc: Muchun Song 
Cc: Oscar Salvador 
Cc: Palmer Dabbelt 
Cc: Pratyush Yadav 
Cc: Richard Weinberger 
Cc: "Ritesh Harjani (IBM)" 
Cc: Russell King 
Cc: Stafford Horne 
Cc: Suren Baghdasaryan 
Cc: Thomas Bogendoerfer 
Cc: Thomas Gleixner 
Cc: Vasily Gorbik 
Cc: Vineet Gupta 
Cc: Vlastimil Babka 
Cc: Will Deacon 
Signed-off-by: Andrew Morton

mips: introduce arch_zone_limits_init()

2026-01-27T04:02:15+00:00

Move calculations of zone limits to a dedicated arch_zone_limits_init()
function.

Later MM core will use this function as an architecture specific callback
during nodes and zones initialization and thus there won't be a need to
call free_area_init() from every architecture.

Link: https://lkml.kernel.org/r/20260111082105.290734-12-rppt@kernel.org
Signed-off-by: Mike Rapoport (Microsoft) 
Cc: Alexander Gordeev 
Cc: Alex Shi 
Cc: Andreas Larsson 
Cc: "Borislav Petkov (AMD)" 
Cc: Catalin Marinas 
Cc: David Hildenbrand 
Cc: David S. Miller 
Cc: Dinh Nguyen 
Cc: Geert Uytterhoeven 
Cc: Guo Ren 
Cc: Heiko Carstens 
Cc: Helge Deller 
Cc: Huacai Chen 
Cc: Ingo Molnar 
Cc: Johannes Berg 
Cc: John Paul Adrian Glaubitz 
Cc: Jonathan Corbet 
Cc: Klara Modin 
Cc: Liam Howlett 
Cc: Lorenzo Stoakes 
Cc: Magnus Lindholm 
Cc: Matt Turner 
Cc: Max Filippov 
Cc: Michael Ellerman 
Cc: Michal Hocko 
Cc: Michal Simek 
Cc: Muchun Song 
Cc: Oscar Salvador 
Cc: Palmer Dabbelt 
Cc: Pratyush Yadav 
Cc: Richard Weinberger 
Cc: "Ritesh Harjani (IBM)" 
Cc: Russell King 
Cc: Stafford Horne 
Cc: Suren Baghdasaryan 
Cc: Thomas Bogendoerfer 
Cc: Thomas Gleixner 
Cc: Vasily Gorbik 
Cc: Vineet Gupta 
Cc: Vlastimil Babka 
Cc: Will Deacon 
Signed-off-by: Andrew Morton