linux-toradex.git/arch/mips/mm/Makefile, branch v3.0.2

MIPS: Move arch_get_unmapped_area and gang to new file.

2011-05-19T08:55:49+00:00

It never really belonged into syscall.c and it's about to become well more
complex.

Signed-off-by: Ralf Baechle

MIPS: Kconfig and Makefile update for Netlogic XLR/XLS

2011-05-19T08:55:40+00:00

Add NLM_XLR_BOARD, CPU_XLR and other config options
Makefile updates, mostly based on r4k

Signed-off-by: Jayachandran C 
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2334/
Signed-off-by: Ralf Baechle

MIPS: Add -Werror to arch/mips/Kbuild

2010-08-05T12:25:44+00:00

Adding subdirs-ccflags-y := -Werror to arch/mips/Kbuild
let us in one go cover all files with -Werror.

In addition this allows us to remove the
individual -Werror definition in various Makefile.

Adding the definition to Kbuild as a recursive
option help us not to forget to do so.

With this change we now compile arch/mips/kernel/cpufreq with -Werror

One drawback:
When specifying a subdirectory covered by the Kbuild file like this:

    make arch/mips/kernel/

then kbuild fails to pick up the -Werror definition.

Signed-off-by: Sam Ravnborg 
To: linux-mips 
To: Wu Zhangjin 
Patchwork: https://patchwork.linux-mips.org/patch/1301/
Signed-off-by: Ralf Baechle

MIPS: Add support files for hugetlbfs.

2009-06-17T10:06:30+00:00

Signed-off-by: David Daney 
Signed-off-by: Ralf Baechle

MIPS: Hook up Cavium OCTEON in arch/mips.

2009-01-11T09:57:22+00:00

Take all the OCTEON specific files that were added, and hook them into
the build system for the arch/mips.  For versions of GCC that lack
OCTEON support, override gas target architecture.

Signed-off-by: Tomaso Paoletti 
Signed-off-by: David Daney 
Signed-off-by: Ralf Baechle

MIPS: Add CONFIG_CPU_R5500 for NEC VR5500 series processors

2008-10-27T16:18:29+00:00

We already have sufficient infrastructure to support VR5500 and VR5500A
series processors.  Here's a Makefile support to make it selectable by
ports, and enable it for NEC EMMA2RH Markeins board.

This patch also fixes a confused target help, and adds 1Gb PageMask bits
supported by VR5500 and its variants.

Signed-off-by: Shinya Kuribayashi 
Signed-off-by: Ralf Baechle

mips: use generic show_mem()

2008-07-26T19:00:11+00:00

Remove arch-specific show_mem() in favor of the generic version.

This also removes the following redundant information display:

	- pages in swapcache, printed by show_swap_cache_info()

where show_mem() calls show_free_areas(), which calls
show_swap_cache_info().

And show_mem() does now actually print something on configurations
with multiple nodes.

Signed-off-by: Johannes Weiner 
Acked-by: Ralf Baechle 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

[MIPS] Reimplement clear_page/copy_page

2008-04-28T16:14:23+00:00

Fold the SB-1 specific implementation of clear_page/copy_page in the
generic version, and rewrite that one in tlbex style. The immediate
benefits:
  - It converts the compile-time workaround for SB-1 pass 1 prefetches
    to a more efficient run-time check.
  - It allows adjustment of loop unfolling, which helps to reduce the
    number of redundant cdex cache ops.
  - It fixes some esoteric cornercases (the cache line length calculations
    can go wrong, and support for 64k pages without prefetch instructions
    will overflow the addiu immediate).
  - Somewhat better guesses of "good" prefetch values.

Signed-off-by: Thiemo Seufer 
Signed-off-by: Ralf Baechle

[MIPS] Split the micro-assembler from tlbex.c.

2008-02-01T14:48:44+00:00

This patch moves the micro-assembler in a separate implementation, as
it is useful for further run-time optimizations. The only change in
behaviour is cutting down printk noise at kernel startup time.

Checkpatch complains about macro parameters which aren't protected by
parentheses. I believe this is a flaw in checkpatch, the paste operator
used in those macros won't work with parenthesised parameters.

Signed-off-by: Thiemo Seufer 
Signed-off-by: Ralf Baechle

[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.

2007-10-11T22:46:05+00:00

It may not be perfect yet but the SB1 code is badly borken and has
horrible performance issues.

Downside: This seriously breaks support for pass 1 parts of the BCM1250
where indexed cacheops don't work quite reliable but I seem to be the
last one on the planet with a pass 1 part anyway.

Signed-off-by: Ralf Baechle