linux-toradex.git/arch/mips/mm/tlbex.c, branch v3.7.9

Revert "MIPS: Optimise TLB handlers for MIPS32/64 R2 cores."

2013-01-17T16:46:43+00:00

commit 9120963578320532dfb3a9a7947e8d05b39900b5 upstream.

This reverts commit ff401e52100dcdc85e572d1ad376d3307b3fe28e.

This breaks on MIPS64 R2 cores such as Broadcom's.

Signed-off-by: Jayachandran C 
Signed-off-by: Greg Kroah-Hartman

MIPS: R5000: Fix TLB hazard handling.

2012-10-16T20:22:23+00:00

R5000 and the Nevada CPUs (RM5230, RM5231, RM5260, RM5261, RM5270 and
RM5271) are basically the same CPU core and all are documented to require
two instructions separating a write to c0_pagemask, c0_entryhi, c0_entrylo0,
c0_entrylo1 or c0_index.

So far we were only providing on cycle before / after a TLBR/TLBWI
for R5000 but 3 cycles before and 1 cycles after for the Nevadas.

Signed-off-by: Ralf Baechle

MIPS: tlbex: Deal with re-definition of label

2012-10-16T20:21:27+00:00

The microassembler used in tlbex.c does not notice if a label is redefined
resulting in relocations against such labels silently missrelocated.
The issues exists since commit add6eb04776db4189ea89f596cbcde31b899be9d
[Synthesize TLB exception handlers at runtime.] in 2.6.10 and went unnoticed
for so long because the relocations for the affected branches got computed
to do something *almost* sensible.

The issue affects R4000, R4400, QED/IDT RM5230, RM5231, RM5260, RM5261,
RM5270 and RM5271 processors.

Signed-off-by: Ralf Baechle

MIPS: Optimize TLB refill for RI/XI configurations.

2012-10-11T09:11:20+00:00

We don't have to do a separate shift to eliminate the software bits,
just rotate them into the fill and they will be ignored.

Signed-off-by: David Daney 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4294/
Signed-off-by: Ralf Baechle

Merge branch 'ralf-3.7' of git://git.linux-mips.org/pub/scm/sjhill/linux-sjhill into mips-for-linux-next

2012-09-28T14:29:55+00:00

MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'.

2012-09-13T22:00:34+00:00

Remove usage of the 'kernel_uses_smartmips_rixi' macro from all files
and use new 'cpu_has_rixi' instead.

Signed-off-by: Steven J. Hill 
Acked-by: David Daney

MIPS: Optimise TLB handlers for MIPS32/64 R2 cores.

2012-09-13T20:43:54+00:00

The EXT and INS instructions can be used to decrease code size and
thus speed up TLB handlers on MIPS32R2 and MIPS64R2 cores.

Signed-off-by: Steven J. Hill

MIPS: Avoid pipeline stalls on some MIPS32R2 cores.

2012-09-13T20:43:52+00:00

The architecture specification says that an EHB instruction is
needed to avoid a hazard when writing TLB entries. However, some
cores do not have this hazard, and thus the EHB instruction causes
a costly pipeline stall. Detect these cores and do not use the EHB
instruction.

Signed-off-by: Steven J. Hill

MIPS: Add support for the M14Kc core.

2012-07-06T21:56:00+00:00

[ralf@linux-mips.org: Fixed whitespace damage.]

Signed-off-by: Steven J. Hill 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3773/
Signed-off-by: Ralf Baechle

Disintegrate asm/system.h for MIPS

2012-03-28T17:30:02+00:00

Disintegrate asm/system.h for MIPS.

Signed-off-by: David Howells 
Acked-by: Ralf Baechle 
cc: linux-mips@linux-mips.org