linux-toradex.git/arch/mips/mti-malta, branch v4.6-rc1

MIPS: Fix early CM probing

2016-02-09T16:18:31+00:00

Commit c014d164f21d ("MIPS: Add platform callback before initializing
the L2 cache") added a platform_early_l2_init function in order to allow
platforms to probe for the CM before L2 initialisation is performed, so
that CM GCRs are available to mips_sc_probe.

That commit actually fails to do anything useful, since it checks
mips_cm_revision to determine whether it should call mips_cm_probe but
the result of mips_cm_revision will always be 0 until mips_cm_probe has
been called. Thus the "early" mips_cm_probe call never occurs.

Fix this & drop the useless weak platform_early_l2_init function by
simply calling mips_cm_probe from setup_arch. For platforms that don't
select CONFIG_MIPS_CM this will be a no-op, and for those that do it
removes the requirement for them to call mips_cm_probe manually
(although doing so isn't harmful for now).

Signed-off-by: Paul Burton 
Reviewed-by: Alexander Sverdlin 
Cc: Andrzej Hajda 
Cc: Aaro Koskinen 
Cc: Masahiro Yamada 
Cc: Rob Herring 
Cc: Peter Hurley 
Cc: Leonid Yegoshin 
Cc: Jaedon Shin 
Cc: James Hogan 
Cc: Jonas Gorski 
Cc: Markos Chandras 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12475/
Signed-off-by: Ralf Baechle

MIPS: Malta: Register UP SMP ops if all else fails

2015-11-11T07:35:49+00:00

If we fail to register any real SMP implementations, fall back to
registering the dummy UP implementation. Otherwise when we build an SMP
kernel & run it on a system where the SMP implementations fail to probe
(eg. QEMU) the kernel will perform a NULL dereference attempting to call
mp_ops->smp_setup() from plat_smp_setup().

Notably this fixes booting kernels with CPS SMP enabled on QEMU, which
doesn't currently implement the CM, CPC or GIC.

Signed-off-by: Paul Burton 
Cc: linux-mips@linux-mips.org
Cc: Peter Hurley 
Cc: Rob Herring 
Cc: linux-kernel@vger.kernel.org
Cc: Markos Chandras 
Patchwork: https://patchwork.linux-mips.org/patch/11223/
Signed-off-by: Ralf Baechle

MIPS: Malta: Setup RAM regions via DT

2015-11-11T07:35:47+00:00

Move memory configuration to be performed via device tree for the Malta
board. This moves more Malta specific code to malta-dtshim.c, leaving
the rest of the mti-malta code a little more board-agnostic. This will
be useful to share more code between boards, with the device tree
providing the board specifics as intended.

Since we can't rely upon Malta boards running a bootloader capable of
handling devictrees & filling in the required information, a piece of
shim code (malta_dt_shim) is added to consume the (e)memsize variables
provided as part of the bootloader environment (or on the kernel command
line) then generate the DT memory node using the provided values.

Signed-off-by: Paul Burton 
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: Kumar Gala 
Cc: linux-kernel@vger.kernel.org
Cc: Ian Campbell 
Cc: Rob Herring 
Cc: James Hogan 
Cc: Pawel Moll 
Cc: Markos Chandras 
Cc: Mark Rutland 
Patchwork: https://patchwork.linux-mips.org/patch/11222/
Signed-off-by: Ralf Baechle

MIPS: Malta: Remove fw_memblock_t abstraction

2015-11-11T07:35:45+00:00

The fw_getmdesc function & fw_memblock_t abstraction is only used by
Malta, and so far as I can tell serves no purpose beyond making the code
less clear than it could be. Remove the useless level of abstraction.

Signed-off-by: Paul Burton 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: James Hogan 
Cc: Markos Chandras 
Patchwork: https://patchwork.linux-mips.org/patch/11221/
Signed-off-by: Ralf Baechle

MIPS: Malta: Split obj-y entries across lines

2015-11-11T07:35:42+00:00

Split the obj-y entries to their own lines such that it's easier to see
what's going on when adding or removing entries.

Signed-off-by: Paul Burton 
Cc: linux-mips@linux-mips.org
Cc: Markos Chandras 
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/11220/
Signed-off-by: Ralf Baechle

MIPS: malta: Use generic platform_maar_init

2015-09-03T10:07:41+00:00

The default implementation of platform_maar_init is sufficient for Malta
boards where we want to allow speculation in the regions of memory
corresponding to DDR & disallow it elsewhere. Drop the custom
implementation such that the default is used, reducing the duplication
of information provided by the Malta platform code.

Signed-off-by: Paul Burton 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: James Hogan 
Cc: Markos Chandras 
Patchwork: https://patchwork.linux-mips.org/patch/10677/
Signed-off-by: Ralf Baechle

MIPS: CM: Add support for reporting CM cache errors

2015-08-26T13:23:15+00:00

The CM cache error reporting code is not Malta specific and as such it
should live in the mips-cm.c file. Moreover, CM2 and CM3 differ in the
way cache errors are being recorded to the registers so extend the
previous code to add support for the CM3 as well.

Signed-off-by: Markos Chandras 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10646/
Signed-off-by: Ralf Baechle

MIPS: Add platform callback before initializing the L2 cache

2015-08-26T13:23:11+00:00

Allow platforms to perform platform-specific steps before configuring
the L2 cache. This is necessary for platforms with CM3 since the L2
parameters no longer live in the Config2 register.

Signed-off-by: Markos Chandras 
Cc: Paul Burton 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10642/
Signed-off-by: Ralf Baechle

MIPS: Export get_c0_perfcount_int()

2015-08-03T07:25:18+00:00

get_c0_perfcount_int is tested from oprofile code. If oprofile is
compiled as module, get_c0_perfcount_int needs to be exported, otherwise
it cannot be resolved.

Fixes: a669efc4a3b4 ("MIPS: Add hook to get C0 performance counter interrupt")
Cc: stable@vger.kernel.org # v3.19+
Signed-off-by: Felix Fietkau 
Cc: linux-mips@linux-mips.org
Cc: abrestic@chromium.org
Patchwork: https://patchwork.linux-mips.org/patch/10763/
Signed-off-by: Ralf Baechle

MIPS: SMP: Don't increment irq_count multiple times for call function IPIs

2015-08-03T07:25:12+00:00

The majority of SMP platforms handle their IPIs through do_IRQ()
which calls irq_{enter/exit}(). When a call function IPI is received,
smp_call_function_interrupt() is called which also calls
irq_{enter,exit}(), meaning irq_count is raised twice.

When tick broadcasting is used (which is implemented via a call
function IPI), this incorrectly causes all CPU idle time on the core
receiving broadcast ticks to be accounted as time spent servicing
IRQs, as account_process_tick() will account as such if irq_count is
greater than 1. This results in 100% CPU usage being reported on a
core which receives its ticks via broadcast.

This patch removes the SMP smp_call_function_interrupt() wrapper which
calls irq_{enter,exit}(). Platforms which handle their IPIs through
do_IRQ() now call generic_smp_call_function_interrupt() directly to
avoid incrementing irq_count a second time. Platforms which don't
(loongson, sgi-ip27, sibyte) call generic_smp_call_function_interrupt()
wrapped in irq_{enter,exit}().

Signed-off-by: Alex Smith 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10770/
Signed-off-by: Ralf Baechle