linux-toradex.git/arch/mips/oprofile/op_model_mipsxx.c, branch v3.2.51 Linux kernel for Apalis and Colibri modules generic-ipi: more merge fallout 2008-07-15T20:08:52+00:00 Ingo Molnar mingo@elte.hu 2008-07-15T20:08:52+00:00 f6f88e9bfb6ced9871ed65ebe85c371de3c9e4be fix more API change fallout in recently merged upstream changes. Signed-off-by: Ingo Molnar <mingo@elte.hu> 
fix more API change fallout in recently merged upstream changes.

Signed-off-by: Ingo Molnar <mingo@elte.hu>
[MIPS] Fix build failure in mips oprofile code 2008-05-12T15:46:56+00:00 Thiemo Seufer ths@networkno.de 2008-05-06T10:23:33+00:00 005ca9a3f1238ffebd9c4d09d581f708277d2985 This patch fixes a warning-as-error induced build failure of 64bit MIPS kernels. Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
This patch fixes a warning-as-error induced build failure of 64bit MIPS
kernels.

Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] unexport null_perf_irq() and make it static 2008-04-28T16:14:31+00:00 Dmitri Vorobiev dmitri.vorobiev@gmail.com 2008-04-01T23:58:38+00:00 46684734dd6a55af09c3fe799af7d74cb938684c This patch unexports the null_perf_irq() symbol, and simultaneously makes this function static. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
This patch unexports the null_perf_irq() symbol, and simultaneously
makes this function static.

Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] Add support for MIPS CMP platform. 2008-04-28T16:14:26+00:00 Ralf Baechle ralf@linux-mips.org 2008-04-28T16:14:26+00:00 39b8d5254246ac56342b72f812255c8f7a74dca9 Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] Extend performance counter event field. 2008-01-29T10:14:59+00:00 Ralf Baechle ralf@linux-mips.org 2008-01-29T10:14:59+00:00 39a51109dd14001185b0cd122ca46cce1d0795bf The latest draft version of the MIPS Architecture Specification extends the 6 bit event field by adding a directly adjacent 4-bit EventExt field for a total of 10 bits. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
The latest draft version of the MIPS Architecture Specification extends the
6 bit event field by adding a directly adjacent 4-bit EventExt field for a
total of 10 bits.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] Oprofile: Fix computation of number of counters. 2007-12-06T17:15:58+00:00 Ralf Baechle ralf@linux-mips.org 2007-12-06T09:12:28+00:00 5e2862eb5a263a0339a85545d96fb20995d67b1f VSMP kernels will split the available performance counters between the two processors / cores. But don't do this when we're not on a VSMP system ... Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
VSMP kernels will split the available performance counters between the two
processors / cores.  But don't do this when we're not on a VSMP system ...

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] Fix "no space between function name and open parenthesis" warnings. 2007-10-11T22:46:15+00:00 Ralf Baechle ralf@linux-mips.org 2007-10-11T22:46:15+00:00 49a89efbbbcc178a39555c43bd59a7593c429664 Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] Allow hardwiring of the CPU type to a single type for optimization. 2007-10-11T22:46:15+00:00 Ralf Baechle ralf@linux-mips.org 2007-10-11T22:46:15+00:00 10cc3529072d5415fb040018a8a99aa7a60190b6 This saves a few k on systems which only ever ship with a single CPU type. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
This saves a few k on systems which only ever ship with a single CPU type.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] Separate performance counter interrupts 2007-06-14T17:25:15+00:00 Chris Dearman chris@mips.com 2007-05-24T21:24:20+00:00 ffe9ee4709cf513fb80e9b7e04d214dd8b76a10d Support for performance counter overflow interrupt that is on a separate interrupt from the timer. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Support for performance counter overflow interrupt that is on a separate
interrupt from the timer.

Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] Fix oprofile logic to physical counter remapping 2007-04-24T21:10:18+00:00 Ralf Baechle ralf@linux-mips.org 2007-04-24T20:42:20+00:00 6f4c5bdef2943d9ec074be32c437ca897016aaad This did cause oprofile to fail on non-multithreaded systems with more than 2 processors such as the BCM1480. Reported by Manish Lachwani (mlachwani@mvista.com). Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
This did cause oprofile to fail on non-multithreaded systems with more
than 2 processors such as the BCM1480.

Reported by Manish Lachwani (mlachwani@mvista.com).

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>