linux-toradex.git/arch/mips/pci, branch v5.1-rc4

Merge tag 'mips_5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

2019-03-05T19:28:25+00:00

Pull MIPS updates from Paul Burton:

 - Support for the MIPSr6 MemoryMapID register & Global INValidate TLB
   (GINVT) instructions, allowing for more efficient TLB maintenance
   when running on a CPU such as the I6500 that supports these.

 - Enable huge page support for MIPS64r6.

 - Optimize post-DMA cache sync by removing that code entirely for
   kernel configurations in which we know it won't be needed.

 - The number of pages allocated for interrupt stacks is now calculated
   correctly, where before we would wastefully allocate too much memory
   in some configurations.

 - The ath79 platform migrates to devicetree.

 - The bcm47xx platform sees fixes for the Buffalo WHR-G54S board.

 - The ingenic/jz4740 platform gains support for appended devicetrees.

 - The cavium_octeon, lantiq, loongson32 & sgi-ip27 platforms all see
   cleanups as do various pieces of core architecture code.

* tag 'mips_5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (66 commits)
  MIPS: lantiq: Remove separate GPHY Firmware loader
  MIPS: ingenic: Add support for appended devicetree
  MIPS: SGI-IP27: rework HUB interrupts
  MIPS: SGI-IP27: do boot CPU init later
  MIPS: SGI-IP27: do xtalk scanning later
  MIPS: SGI-IP27: use pr_info/pr_emerg and pr_cont to fix output
  MIPS: SGI-IP27: clean up bridge access and header files
  MIPS: SGI-IP27: get rid of volatile and hubreg_t
  MIPS: irq: Allocate accurate order pages for irq stack
  MIPS: dma-noncoherent: Remove bogus condition in dma_sync_phys()
  MIPS: eBPF: Remove REG_32BIT_ZERO_EX
  MIPS: eBPF: Always return sign extended 32b values
  MIPS: CM: Fix indentation
  MIPS: BCM47XX: Fix/improve Buffalo WHR-G54S support
  MIPS: OCTEON: program rx/tx-delay always from DT
  MIPS: OCTEON: delete board-specific link status
  MIPS: OCTEON: don't lie about interface type of CN3005 board
  MIPS: OCTEON: warn if deprecated link status is being used
  MIPS: OCTEON: add fixed-link nodes to in-kernel device tree
  MIPS: Delete unused flush_cache_sigtramp()
  ...

MIPS: SGI-IP27: rework HUB interrupts

2019-02-19T20:46:03+00:00

This commit rearranges the HUB interrupt code by using MIPS_IRQ_CPU
interrupt handling code and modern Linux IRQ framework features to get
rid of global arrays. It also adds support for irq affinity setting.

Signed-off-by: Thomas Bogendoerfer 
Signed-off-by: Paul Burton 
Cc: Ralf Baechle 
Cc: James Hogan 
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org

MIPS: SGI-IP27: clean up bridge access and header files

2019-02-19T20:46:02+00:00

Introduced bridge_read/bridge_write/bridge_set/bridge_clr for accessing
bridge register and get rid of volatile declarations. Also removed
all typedefs from arch/mips/include/asm/pci/bridge.h and cleaned up
language in arch/mips/pci/ops-bridge.c

Signed-off-by: Thomas Bogendoerfer 
Signed-off-by: Paul Burton 
Cc: Ralf Baechle 
Cc: James Hogan 
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org

MIPS: OCTEON: don't set octeon_dma_bar_type if PCI is disabled

2019-01-29T19:47:02+00:00

Don't set octeon_dma_bar_type if PCI is disabled. This avoids creation
of the MSI irqchip later on, and saves a bit of memory.

Signed-off-by: Aaro Koskinen 
Signed-off-by: Paul Burton 
Fixes: a214720cbf50 ("Disable MSI also when pcie-octeon.pcie_disable on")
Cc: stable@vger.kernel.org # v3.3+
Cc: linux-mips@vger.kernel.org

MIPS: ath79: drop legacy pci code

2019-01-22T19:17:22+00:00

With the target now being fully OF based, we can drop the legacy pci
platform code. The only bits that we need to keep is the fixup code
which we move to its own code file.

Signed-off-by: John Crispin 
Signed-off-by: Paul Burton 
Cc: Ralf Baechle 
Cc: James Hogan 
Cc: Rob Herring 
Cc: Pengutronix Kernel Team 
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: Felix Fietkau

Disable MSI also when pcie-octeon.pcie_disable on

2019-01-10T18:57:13+00:00

Octeon has an boot-time option to disable pcie.

Since MSI depends on PCI-E, we should also disable MSI also with
this option is on in order to avoid inadvertently accessing PCIe
registers.

Signed-off-by: YunQiang Su 
Signed-off-by: Paul Burton 
Cc: pburton@wavecomp.com
Cc: linux-mips@vger.kernel.org
Cc: aaro.koskinen@iki.fi
Cc: stable@vger.kernel.org # v3.3+

MIPS: Use device_type helpers to access the node type

2018-11-19T19:04:38+00:00

Remove directly accessing device_node.type pointer and use the accessors
instead. This will eventually allow removing the type pointer.

Signed-off-by: Rob Herring 
Signed-off-by: Paul Burton 
Patchwork: https://patchwork.linux-mips.org/patch/21150/
Cc: Ralf Baechle 
Cc: James Hogan 
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org

MIPS: SiByte: Set 32-bit bus mask for BCM1250 PCI

2018-11-15T18:57:44+00:00

The Broadcom SiByte BCM1250, BCM1125H and BCM1125 SOCs have an onchip
32-bit PCI host bridge, and the two former SOCs also have an onchip HT
host bridge.  The HT host bridge, where present, appears in the PCI
configuration space as if it was a device on the 32-bit PCI bus behind
the PCI host bridge, however at the hardware level its signals are
routed separately, so these two devices are actually peer host bridges.

As documented[1] and observed in reality the 32-bit PCI host bridge does
not support 64-bit addressing as it does not support the Dual Address
Cycle (DAC) PCI command, and naturally, being 32-bit only, it has no
means to carry the high 32 address bits otherwise.  However the DRAM
controller also included in the SOC supports memory amounts of up to
16GiB, and due to how the address decoder has been wired in the SOC any
memory beyond 1GiB is actually mapped starting from 4GiB physical up,
that is beyond the 32-bit addressable limit.  Consequently if the
maximum amount of memory has been installed, then it will span up to
19GiB.

Contrariwise, the HT host bridge does support full 40-bit addressing
defined by the HyperTransport (formerly LDT) specification the bridge
adheres to, depending on the peripherals revision of the SOC[2] either
revision 0.17[3] or revision 1.03[4].  This allows addressing any and
all memory installed, and well beyond.

Set the bus mask then to limit DMA addressing to 32 bits for all the
devices down the 32-bit PCI host bridge, excluding however any devices
that are down the HT host bridge.

References:

[1] "BCM1250/BCM1125/BCM1125H User Manual", Revision 1250_1125-UM100-R,
    Broadcom Corporation, 21 Oct 2002, Section 8: "PCI Bus and
    HyperTransport Fabric", "Introduction", p. 190

[2] same, Table 140: "HyperTransport Configuration Header (Type 1)", p.
    245

[3] "Lightning Data Transport IO Specification", Revision 0.17, Advanced
    Micro Devices, 21 Jan 2000, Section 3.2.1.2 "Command Packet", p. 8

[4] "HyperTransport I/O Link Specification", Revision 1.03,
    HyperTransport Technology Consortium, 10 Oct 2001, Section 3.2.1.2
    "Request Packet", pp. 27-28

Signed-off-by: Maciej W. Rozycki 
Signed-off-by: Paul Burton 
Reviewed-by: Christoph Hellwig 
Patchwork: https://patchwork.linux-mips.org/patch/21106/
Cc: Ralf Baechle 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org

mm: remove include/linux/bootmem.h

2018-10-31T15:54:16+00:00

Move remaining definitions and declarations from include/linux/bootmem.h
into include/linux/memblock.h and remove the redundant header.

The includes were replaced with the semantic patch below and then
semi-automated removal of duplicated '#include 

@@
@@
- #include 
+ #include 

[sfr@canb.auug.org.au: dma-direct: fix up for the removal of linux/bootmem.h]
  Link: http://lkml.kernel.org/r/20181002185342.133d1680@canb.auug.org.au
[sfr@canb.auug.org.au: powerpc: fix up for removal of linux/bootmem.h]
  Link: http://lkml.kernel.org/r/20181005161406.73ef8727@canb.auug.org.au
[sfr@canb.auug.org.au: x86/kaslr, ACPI/NUMA: fix for linux/bootmem.h removal]
  Link: http://lkml.kernel.org/r/20181008190341.5e396491@canb.auug.org.au
Link: http://lkml.kernel.org/r/1536927045-23536-30-git-send-email-rppt@linux.vnet.ibm.com
Signed-off-by: Mike Rapoport 
Signed-off-by: Stephen Rothwell 
Acked-by: Michal Hocko 
Cc: Catalin Marinas 
Cc: Chris Zankel 
Cc: "David S. Miller" 
Cc: Geert Uytterhoeven 
Cc: Greentime Hu 
Cc: Greg Kroah-Hartman 
Cc: Guan Xuetao 
Cc: Ingo Molnar 
Cc: "James E.J. Bottomley" 
Cc: Jonas Bonn 
Cc: Jonathan Corbet 
Cc: Ley Foon Tan 
Cc: Mark Salter 
Cc: Martin Schwidefsky 
Cc: Matt Turner 
Cc: Michael Ellerman 
Cc: Michal Simek 
Cc: Palmer Dabbelt 
Cc: Paul Burton 
Cc: Richard Kuo 
Cc: Richard Weinberger 
Cc: Rich Felker 
Cc: Russell King 
Cc: Serge Semin 
Cc: Thomas Gleixner 
Cc: Tony Luck 
Cc: Vineet Gupta 
Cc: Yoshinori Sato 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

MIPS/PCI: Let Loongson-3 pci_ops access extended config space

2018-09-20T01:57:30+00:00

Original Loongson-3 pci_ops can only access standard pci config space,
this patch let it be able to access extended pci config space.

Signed-off-by: Huacai Chen 
[paul.burton@mips.com: Tweaks to fix checkpatch warnings, reverse xmas tree]
Signed-off-by: Paul Burton 
Patchwork: https://patchwork.linux-mips.org/patch/20707/
Cc: Ralf Baechle 
Cc: James Hogan 
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang 
Cc: Zhangjin Wu 
Cc: Huacai Chen