linux-toradex.git/arch/openrisc/kernel, branch v4.15

Merge tag 'for-linus' of git://github.com/openrisc/linux

2017-11-13T20:12:00+00:00

Pull OpenRISC updates from Stafford Horne:
 "The OpenRISC work is a bit more interesting this time, adding SMP
  support and a few general cleanups.

  Small Things:

   - Move OpenRISC docs into Documentation and clean them up

   - Document previously undocumented devicetree bindings

   - Update the or1ksim dts to use stdout-path

  OpenRISC SMP support details:

   - First the "use shadow registers" and "define CPU_BIG_ENDIAN as
     true" get the architecture ready for SMP.

   - The "add 1 and 2 byte cmpxchg support" and "use qspinlocks and
     qrwlocks" add the SMP locking infrastructure as needed. Using the
     qspinlocks and qrwlocks as suggested by Peter Z while reviewing the
     original spinlocks implementation.

   - The "support for ompic" adds a new irqchip device which is used for
     IPI communication to support SMP.

   - The "initial SMP support" adds smp.c and makes changes to all of
     the necessary data-structures to be per-cpu.

  The remaining patches are bug fixes and debug helpers which I wanted
  to keep separate from the "initial SMP support" in order to allow them
  to be reviewed on their own. This includes:

   - add cacheflush support to fix icache aliasing

   - fix initial preempt state for secondary cpu tasks

   - sleep instead of spin on secondary wait

   - support framepointers and STACKTRACE_SUPPORT

   - enable LOCKDEP_SUPPORT and irqflags tracing

   - timer sync: Add tick timer sync logic

   - fix possible deadlock in timer sync, pointed out by mips guys

  Note: the irqchip patch was reviewed with Marc and we agreed to push
  it together with these patches"

* tag 'for-linus' of git://github.com/openrisc/linux:
  openrisc: fix possible deadlock scenario during timer sync
  openrisc: pass endianness info to sparse
  openrisc: add tick timer multi-core sync logic
  openrisc: enable LOCKDEP_SUPPORT and irqflags tracing
  openrisc: support framepointers and STACKTRACE_SUPPORT
  openrisc: add simple_smp dts and defconfig for simulators
  openrisc: add cacheflush support to fix icache aliasing
  openrisc: sleep instead of spin on secondary wait
  openrisc: fix initial preempt state for secondary cpu tasks
  openrisc: initial SMP support
  irqchip: add initial support for ompic
  dt-bindings: add openrisc to vendor prefixes list
  openrisc: use qspinlocks and qrwlocks
  openrisc: add 1 and 2 byte cmpxchg support
  openrisc: use shadow registers to save regs on exception
  dt-bindings: openrisc: Add OpenRISC platform SoC
  Documentation: openrisc: Updates to README
  Documentation: Move OpenRISC docs out of arch/
  MAINTAINERS: Add OpenRISC pic maintainer
  openrisc: dts: or1ksim: Add stdout-path

openrisc: fix possible deadlock scenario during timer sync

2017-11-03T05:01:17+00:00

OpenRISC borrows its timer sync logic from MIPS, Matt helped to review
the OpenRISC implementation and noted that we may suffer the same
deadlock case that MIPS has faced. The case being:

  "the MIPS timer synchronization code contained the possibility of
  deadlock. If you mark a CPU online before it goes into the synchronize
  loop, then the boot CPU can schedule a different thread and send IPIs to
  all "online" CPUs. It gets stuck waiting for the secondary to ack it's
  IPI, since this secondary CPU has not enabled IRQs yet, and is stuck
  waiting for the master to synchronise with it.  The system then
  deadlocks."

Fix this by moving set_cpu_online() to after timer sync.

Reported-by: Matt Redfearn 
Signed-off-by: Stafford Horne

openrisc: add tick timer multi-core sync logic

2017-11-03T05:01:16+00:00

In case timers are not in sync when cpus start (i.e. hot plug / offset
resets) we need to synchronize the secondary cpus internal timer with
the main cpu.  This is needed as in OpenRISC SMP there is only one
clocksource registered which reads from the same ttcr register on each
cpu.

This synchronization routine heavily borrows from mips implementation that
does something similar.

Signed-off-by: Stafford Horne

openrisc: enable LOCKDEP_SUPPORT and irqflags tracing

2017-11-03T05:01:16+00:00

Lockdep is needed for proving the spinlocks and rwlocks work fine on our
platform.  It also requires calling the trace_hardirqs_off() and
trace_hardirqs_on() pair of routines when entering and exiting an
interrupt.

For OpenRISC the interrupt stack frame does not support frame pointers,
so to call trace_hardirqs_on() and trace_hardirqs_off() here the macro's
build up a stack frame each time.

There is one necessary small change in _sys_call_handler to move
interrupt enabling later so they can get re-enabled during syscall
restart. This was done to fix lockdep warnings that are now possible due
to this
patch.

Signed-off-by: Stafford Horne

openrisc: support framepointers and STACKTRACE_SUPPORT

2017-11-03T05:01:15+00:00

For lockdep support a reliable stack trace mechanism is needed.  This
patch adds support in OpenRISC for the stacktrace framework, implemented
by a simple unwinder api.  The unwinder api supports both framepointer
and basic stack tracing.

The unwinder is now used to replace the stack_dump() implementation as
well. The new traces are inline with other architectures trace format:

 Call trace:
 [] show_stack+0x3c/0x58
 [] dump_stack+0xa8/0xe4
 [] __cpu_up+0x64/0x130
 [] bringup_cpu+0x3c/0x178
 [] cpuhp_invoke_callback+0xa8/0x1fc
 [] cpuhp_up_callbacks+0x44/0x14c
 [] cpu_up+0x14c/0x1bc
 [] smp_init+0x104/0x15c
 [] ? kernel_init+0x0/0x140
 [] kernel_init_freeable+0xbc/0x25c
 [] ? kernel_init+0x0/0x140
 [] kernel_init+0x1c/0x140
 [] ? schedule_tail+0x18/0xa0
 [] ret_from_fork+0x1c/0x9c

Signed-off-by: Stafford Horne

openrisc: add cacheflush support to fix icache aliasing

2017-11-03T05:01:15+00:00

On OpenRISC the icache does not snoop data stores.  This can cause
aliasing as reported by Jan. This patch fixes the issue to ensure icache
is properly synchronized when code is written to memory.  It supports both
SMP and UP flushing.

This supports dcache flush as well for architectures that do not support
write-through caches; most OpenRISC implementations do implement
write-through cache however. Dcache flushes are done only on a single
core as OpenRISC dcaches all support snooping of bus stores.

Signed-off-by: Jan Henrik Weinstock 
[shorne@gmail.com: Squashed patches and wrote commit message]
Signed-off-by: Stafford Horne

openrisc: sleep instead of spin on secondary wait

2017-11-03T05:01:14+00:00

Currently we do a spin on secondary cpus when waiting to boot.  This
theoretically causes issues with power consumption and does cause issues
with qemu cycle burning (it starves cpu 0 from actually being able to
boot.)

This change puts each secondary cpu to sleep if they have a power
management unit, then signals them to wake via IPI when its time to boot.
If the cpus have no power management unit they will loop as before.

Note: The wakeup IPI requires a special interrupt handler as on secondary
cpu's the interrupt infrastructure is not yet established.  This
interrupt handler is set and reset by updating SPR_EVBAR.

Signed-off-by: Stafford Horne

openrisc: fix initial preempt state for secondary cpu tasks

2017-11-03T05:01:14+00:00

During SMP testing we were getting the below warning after booting the
secondary cpu:

[    0.060000] BUG: scheduling while atomic: swapper/1/0/0x00000000

This change follows similar patterns from other architectures to start
the schduler with preempt disabled.

Signed-off-by: Stafford Horne

openrisc: initial SMP support

2017-11-03T05:01:13+00:00

This patch introduces the SMP support for the OpenRISC architecture.
The SMP architecture requires cores which have multi-core features which
have been introduced a few years back including:

 - New SPRS SPR_COREID SPR_NUMCORES
 - Shadow SPRs
 - Atomic Instructions
 - Cache Coherency
 - A wired in IPI controller

This patch adds all of the SMP specific changes to core infrastructure,
it looks big but it needs to go all together as its hard to split this
one up.

Boot loader spinning of second cpu is not supported yet, it's assumed
that Linux is booted straight after cpu reset.

The bulk of these changes are trivial changes to refactor to use per cpu
data structures throughout.  The addition of the smp.c and changes in
time.c are the changes.  Some specific notes:

MM changes
----------
The reason why this is created as an array, and not with DEFINE_PER_CPU
is that doing it this way, we'll save a load in the tlb-miss handler
(the load from __per_cpu_offset).

TLB Flush
---------
The SMP implementation of flush_tlb_* works by sending out a
function-call IPI to all the non-local cpus by using the generic
on_each_cpu() function.

Currently, all flush_tlb_* functions will result in a flush_tlb_all(),
which has always been the behaviour in the UP case.

CPU INFO
--------
This creates a per cpu cpuinfo struct and fills it out accordingly for
each activated cpu.  show_cpuinfo is also updated to reflect new version
information in later versions of the spec.

SMP API
-------
This imitates the arm64 implementation by having a smp_cross_call
callback that can be set by set_smp_cross_call to initiate an IPI and a
handle_IPI function that is expected to be called from an IPI irqchip
driver.

Signed-off-by: Stefan Kristiansson 
[shorne@gmail.com: added cpu stop, checkpatch fixes, wrote commit message]
Signed-off-by: Stafford Horne

openrisc: use shadow registers to save regs on exception

2017-11-03T05:01:11+00:00

Previously, the area between 0x0-0x100 have been used as a "scratch"
memory area to temporarily store regs during exception entry. In a
multi-core environment, this will not work.

This change is to use shadow registers for nested context.

Currently only the "critical" temp load/stores are covered, the
EMERGENCY_PRINT ones are left as is (when they are used, it's game over
anyway), they need to be handled as well in the future.

Signed-off-by: Stefan Kristiansson 
Signed-off-by: Stafford Horne