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<title>linux-toradex.git/arch/parisc/kernel/cache.c, branch v3.4.2</title>
<subtitle>Linux kernel for Apalis and Colibri modules</subtitle>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/'/>
<entry>
<title>Disintegrate asm/system.h for PA-RISC</title>
<updated>2012-03-28T17:30:02+00:00</updated>
<author>
<name>David Howells</name>
<email>dhowells@redhat.com</email>
</author>
<published>2012-03-28T17:30:02+00:00</published>
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<id>527dcdccd60759ee38e6224c93f87a6194d970ad</id>
<content type='text'>
Disintegrate asm/system.h for PA-RISC.

Signed-off-by: David Howells &lt;dhowells@redhat.com&gt;
cc: linux-parisc@vger.kernel.org
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<pre>
Disintegrate asm/system.h for PA-RISC.

Signed-off-by: David Howells &lt;dhowells@redhat.com&gt;
cc: linux-parisc@vger.kernel.org
</pre>
</div>
</content>
</entry>
<entry>
<title>[PARISC] prevent speculative re-read on cache flush</title>
<updated>2011-04-15T17:55:56+00:00</updated>
<author>
<name>James Bottomley</name>
<email>James.Bottomley@HansenPartnership.com</email>
</author>
<published>2011-04-15T17:37:22+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=b7d45818444a31948cfc7849136013a0ea54b2fb'/>
<id>b7d45818444a31948cfc7849136013a0ea54b2fb</id>
<content type='text'>
According to Appendix F, the TLB is the primary arbiter of speculation.
Thus, if a page has a TLB entry, it may be speculatively read into the
cache.  On linux, this can cause us incoherencies because if we're about
to do a disk read, we call get_user_pages() to do the flush/invalidate
in user space, but we still potentially have the user TLB entries, and
the cache could speculate the lines back into userspace (thus causing
stale data to be used).  This is fixed by purging the TLB entries before
we flush through the tmpalias space.  Now, the only way the line could
be re-speculated is if the user actually tries to touch it (which is not
allowed).

Signed-off-by: James Bottomley &lt;James.Bottomley@suse.de&gt;
</content>
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<pre>
According to Appendix F, the TLB is the primary arbiter of speculation.
Thus, if a page has a TLB entry, it may be speculatively read into the
cache.  On linux, this can cause us incoherencies because if we're about
to do a disk read, we call get_user_pages() to do the flush/invalidate
in user space, but we still potentially have the user TLB entries, and
the cache could speculate the lines back into userspace (thus causing
stale data to be used).  This is fixed by purging the TLB entries before
we flush through the tmpalias space.  Now, the only way the line could
be re-speculated is if the user actually tries to touch it (which is not
allowed).

Signed-off-by: James Bottomley &lt;James.Bottomley@suse.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>parisc: flush pages through tmpalias space</title>
<updated>2011-01-15T14:44:40+00:00</updated>
<author>
<name>James Bottomley</name>
<email>James.Bottomley@HansenPartnership.com</email>
</author>
<published>2010-12-22T16:22:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=f311847c2fcebd81912e2f0caf8a461dec28db41'/>
<id>f311847c2fcebd81912e2f0caf8a461dec28db41</id>
<content type='text'>
The kernel has an 8M tmpailas space (originally designed for copying
and clearing pages but now only used for clearing).  The idea is
to place zeros into the cache above a physical page rather than into
the physical page and flush the cache, because often the zeros end up
being replaced quickly anyway.

We can also use the tmpalias space for flushing a page.  The difference
here is that we have to do tmpalias processing in the non access data and
instruction traps.  The principle is the same: as long as we know the physical
address and have a virtual address congruent to the real one, the flush will
be effective.

In order to use the tmpalias space, the icache miss path has to be enhanced to
check for the alias region to make the fic instruction effective.

Signed-off-by: James Bottomley &lt;James.Bottomley@suse.de&gt;
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<pre>
The kernel has an 8M tmpailas space (originally designed for copying
and clearing pages but now only used for clearing).  The idea is
to place zeros into the cache above a physical page rather than into
the physical page and flush the cache, because often the zeros end up
being replaced quickly anyway.

We can also use the tmpalias space for flushing a page.  The difference
here is that we have to do tmpalias processing in the non access data and
instruction traps.  The principle is the same: as long as we know the physical
address and have a virtual address congruent to the real one, the flush will
be effective.

In order to use the tmpalias space, the icache miss path has to be enhanced to
check for the alias region to make the fic instruction effective.

Signed-off-by: James Bottomley &lt;James.Bottomley@suse.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>parisc: remove trailing space in messages</title>
<updated>2010-03-06T22:54:09+00:00</updated>
<author>
<name>Frans Pop</name>
<email>elendil@planet.nl</email>
</author>
<published>2010-02-06T17:47:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=a3bee03e718c9251456676b71a723a34c999e891'/>
<id>a3bee03e718c9251456676b71a723a34c999e891</id>
<content type='text'>
Signed-off-by: Frans Pop &lt;elendil@planet.nl&gt;
Cc: linux-parisc@vger.kernel.org
Cc: Kyle McMartin &lt;kyle@mcmartin.ca&gt;
Cc: Helge Deller &lt;deller@gmx.de&gt;
Signed-off-by: Kyle McMartin &lt;kyle@mcmartin.ca&gt;
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Signed-off-by: Frans Pop &lt;elendil@planet.nl&gt;
Cc: linux-parisc@vger.kernel.org
Cc: Kyle McMartin &lt;kyle@mcmartin.ca&gt;
Cc: Helge Deller &lt;deller@gmx.de&gt;
Signed-off-by: Kyle McMartin &lt;kyle@mcmartin.ca&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MM: Pass a PTE pointer to update_mmu_cache() rather than the PTE itself</title>
<updated>2010-02-20T16:41:46+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2009-12-18T16:40:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=4b3073e1c53a256275f1079c0fbfbe85883d9275'/>
<id>4b3073e1c53a256275f1079c0fbfbe85883d9275</id>
<content type='text'>
On VIVT ARM, when we have multiple shared mappings of the same file
in the same MM, we need to ensure that we have coherency across all
copies.  We do this via make_coherent() by making the pages
uncacheable.

This used to work fine, until we allowed highmem with highpte - we
now have a page table which is mapped as required, and is not available
for modification via update_mmu_cache().

Ralf Beache suggested getting rid of the PTE value passed to
update_mmu_cache():

  On MIPS update_mmu_cache() calls __update_tlb() which walks pagetables
  to construct a pointer to the pte again.  Passing a pte_t * is much
  more elegant.  Maybe we might even replace the pte argument with the
  pte_t?

Ben Herrenschmidt would also like the pte pointer for PowerPC:

  Passing the ptep in there is exactly what I want.  I want that
  -instead- of the PTE value, because I have issue on some ppc cases,
  for I$/D$ coherency, where set_pte_at() may decide to mask out the
  _PAGE_EXEC.

So, pass in the mapped page table pointer into update_mmu_cache(), and
remove the PTE value, updating all implementations and call sites to
suit.

Includes a fix from Stephen Rothwell:

  sparc: fix fallout from update_mmu_cache API change

  Signed-off-by: Stephen Rothwell &lt;sfr@canb.auug.org.au&gt;

Acked-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
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<pre>
On VIVT ARM, when we have multiple shared mappings of the same file
in the same MM, we need to ensure that we have coherency across all
copies.  We do this via make_coherent() by making the pages
uncacheable.

This used to work fine, until we allowed highmem with highpte - we
now have a page table which is mapped as required, and is not available
for modification via update_mmu_cache().

Ralf Beache suggested getting rid of the PTE value passed to
update_mmu_cache():

  On MIPS update_mmu_cache() calls __update_tlb() which walks pagetables
  to construct a pointer to the pte again.  Passing a pte_t * is much
  more elegant.  Maybe we might even replace the pte argument with the
  pte_t?

Ben Herrenschmidt would also like the pte pointer for PowerPC:

  Passing the ptep in there is exactly what I want.  I want that
  -instead- of the PTE value, because I have issue on some ppc cases,
  for I$/D$ coherency, where set_pte_at() may decide to mask out the
  _PAGE_EXEC.

So, pass in the mapped page table pointer into update_mmu_cache(), and
remove the PTE value, updating all implementations and call sites to
suit.

Includes a fix from Stephen Rothwell:

  sparc: fix fallout from update_mmu_cache API change

  Signed-off-by: Stephen Rothwell &lt;sfr@canb.auug.org.au&gt;

Acked-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>parisc: ensure broadcast tlb purge runs single threaded</title>
<updated>2009-07-03T03:34:09+00:00</updated>
<author>
<name>Helge Deller</name>
<email>deller@gmx.de</email>
</author>
<published>2009-06-16T20:51:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=e82a3b75127188f20c7780bec580e148beb29da7'/>
<id>e82a3b75127188f20c7780bec580e148beb29da7</id>
<content type='text'>
The TLB flushing functions on hppa, which causes PxTLB broadcasts on the system
bus, needs to be protected by irq-safe spinlocks to avoid irq handlers to deadlock
the kernel. The deadlocks only happened during I/O intensive loads and triggered
pretty seldom, which is why this bug went so long unnoticed.

Signed-off-by: Helge Deller &lt;deller@gmx.de&gt;
[edited to use spin_lock_irqsave on UP as well since we'd been locking there
 all this time anyway, --kyle]
Signed-off-by: Kyle McMartin &lt;kyle@mcmartin.ca&gt;
</content>
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<pre>
The TLB flushing functions on hppa, which causes PxTLB broadcasts on the system
bus, needs to be protected by irq-safe spinlocks to avoid irq handlers to deadlock
the kernel. The deadlocks only happened during I/O intensive loads and triggered
pretty seldom, which is why this bug went so long unnoticed.

Signed-off-by: Helge Deller &lt;deller@gmx.de&gt;
[edited to use spin_lock_irqsave on UP as well since we'd been locking there
 all this time anyway, --kyle]
Signed-off-by: Kyle McMartin &lt;kyle@mcmartin.ca&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>parisc: remove CVS keywords</title>
<updated>2009-07-03T03:34:06+00:00</updated>
<author>
<name>Alexander Beregalov</name>
<email>a.beregalov@gmail.com</email>
</author>
<published>2009-04-03T01:49:22+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=071327ec9005e9a826d088d37021ed2c88e683f7'/>
<id>071327ec9005e9a826d088d37021ed2c88e683f7</id>
<content type='text'>
Signed-off-by: Alexander Beregalov &lt;a.beregalov@gmail.com&gt;
Acked-by: Matthew Wilcox &lt;willy@linux.intel.com&gt;
Acked-by: Grant Grundler &lt;grundler@parisc-linux.org&gt;
Signed-off-by: Kyle McMartin &lt;kyle@mcmartin.ca&gt;
</content>
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<pre>
Signed-off-by: Alexander Beregalov &lt;a.beregalov@gmail.com&gt;
Acked-by: Matthew Wilcox &lt;willy@linux.intel.com&gt;
Acked-by: Grant Grundler &lt;grundler@parisc-linux.org&gt;
Signed-off-by: Kyle McMartin &lt;kyle@mcmartin.ca&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>parisc: BUG_ON() cleanup</title>
<updated>2009-03-13T05:16:35+00:00</updated>
<author>
<name>Helge Deller</name>
<email>deller@gmx.de</email>
</author>
<published>2009-01-06T11:57:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=8980a7baf93e478205e32ec7d6ef3bfb6c0bdfa7'/>
<id>8980a7baf93e478205e32ec7d6ef3bfb6c0bdfa7</id>
<content type='text'>
- convert a few "if (xx) BUG();" to BUG_ON(xx)
- remove a few printk()s, as we get a backtrace with BUG_ON() anyway

Signed-off-by: Helge Deller &lt;deller@gmx.de&gt;
Signed-off-by: Kyle McMartin &lt;kyle@mcmartin.ca&gt;
</content>
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<pre>
- convert a few "if (xx) BUG();" to BUG_ON(xx)
- remove a few printk()s, as we get a backtrace with BUG_ON() anyway

Signed-off-by: Helge Deller &lt;deller@gmx.de&gt;
Signed-off-by: Kyle McMartin &lt;kyle@mcmartin.ca&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>on_each_cpu(): kill unused 'retry' parameter</title>
<updated>2008-06-26T09:24:38+00:00</updated>
<author>
<name>Jens Axboe</name>
<email>jens.axboe@oracle.com</email>
</author>
<published>2008-05-09T07:39:44+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=15c8b6c1aaaf1c4edd67e2f02e4d8e1bd1a51c0d'/>
<id>15c8b6c1aaaf1c4edd67e2f02e4d8e1bd1a51c0d</id>
<content type='text'>
It's not even passed on to smp_call_function() anymore, since that
was removed. So kill it.

Acked-by: Jeremy Fitzhardinge &lt;jeremy.fitzhardinge@citrix.com&gt;
Reviewed-by: Paul E. McKenney &lt;paulmck@linux.vnet.ibm.com&gt;
Signed-off-by: Jens Axboe &lt;jens.axboe@oracle.com&gt;
</content>
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<pre>
It's not even passed on to smp_call_function() anymore, since that
was removed. So kill it.

Acked-by: Jeremy Fitzhardinge &lt;jeremy.fitzhardinge@citrix.com&gt;
Reviewed-by: Paul E. McKenney &lt;paulmck@linux.vnet.ibm.com&gt;
Signed-off-by: Jens Axboe &lt;jens.axboe@oracle.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arch/parisc/: Spelling fixes</title>
<updated>2008-02-03T14:58:20+00:00</updated>
<author>
<name>Joe Perches</name>
<email>joe@perches.com</email>
</author>
<published>2008-02-03T14:58:20+00:00</published>
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<content type='text'>
Signed-off-by: Joe Perches &lt;joe@perches.com&gt;
Signed-off-by: Adrian Bunk &lt;bunk@kernel.org&gt;
</content>
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<pre>
Signed-off-by: Joe Perches &lt;joe@perches.com&gt;
Signed-off-by: Adrian Bunk &lt;bunk@kernel.org&gt;
</pre>
</div>
</content>
</entry>
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