linux-toradex.git/arch/parisc/kernel/pacache.S, branch v4.2.7

parisc: Use unshadowed index register for flush instructions in flush_dcache_page_asm and flush_icache_page_asm

2013-06-18T18:29:10+00:00

The comment at the start of pacache.S states that the base and index
registers used for fdc,fic, and pdc instructions should not use shadowed
registers. Although this is probably unnecessary for tmpalias flushes,
there is also no reason not to comply.

Signed-off-by: John David Anglin 
Signed-off-by: Helge Deller

parisc: use PAGE_SHIFT instead of hardcoded value 12 in pacache.S

2013-05-24T20:30:28+00:00

additionally clean up some whitespaces & tabs.

Signed-off-by: Helge Deller

parisc: fix partly 16/64k PAGE_SIZE boot

2013-05-06T21:08:32+00:00

This patch fixes partly PAGE_SIZEs of 16K or 64K by adjusting the
assembler PTE lookup code and the assembler TEMPALIAS code.  Furthermore
some data alignments for PAGE_SIZE have been limited to 4K (or less) to
not waste too much memory with greater page sizes. As a side note, the
palo loader can (currently) only handle up to 10 ELF segments which is
fixed with tighter aligning as well.

My testings indicated that the ldci command in the sba iommu coding
needed adjustment by the PAGE_SHIFT value and that the I/O PDIR Page
size was only set to 4K for my machine (C3000).

All this fixes partly the boot, but there are still quite some caching
problems left.  Examples are e.g. the symbios logic driver which is
failing:

sym0: <896> rev 0x7 at pci 0000:00:0f.0 irq 69
sym0: PA-RISC Firmware, ID 7, Fast-40, SE, parity checking
CACHE TEST FAILED: DMA error (dstat=0x81).sym0: CACHE INCORRECTLY CONFIGURED.

and the tulip network driver which doesn't seem to work correctly
either:

Sending BOOTP requests .net eth0: Setting full-duplex based on MII#1
link partner capability of 05e1
..... timed out!

Beside those kernel fixes glibc will need fixes too to be able to handle
>4K page sizes.

Signed-off-by: Helge Deller

parisc: fixes and cleanups in page cache flushing (2/4)

2013-02-20T21:49:29+00:00

Implement clear_page_asm and copy_page_asm. These are optimized routines to
clear and copy a page.  I tested prefetch optimizations in clear_page_asm and
copy_page_asm but didn't see any significant performance improvement on rp3440.
I'm not sure if these are routines are significantly faster than memset and/or
memcpy, but they are there for further performance evaluation.

TLB purge operations on PA 1.X SMP machines are now serialized with the help of
the new tlb_lock() and tlb_unlock() macros, since on some PA-RISC machines, TLB
purges need to be serialized in software.  Obviously, lock isn't needed in UP
kernels.  On PA 2.0 machines, there is a local TLB instruction which is much
less disruptive to the memory subsystem.  No lock is needed for local purge.

Loops are also unrolled in flush_instruction_cache_local and
flush_data_cache_local.

The implementation of what used to be copy_user_page (now copy_user_page_asm)
is now fixed. Additionally 64-bit support is now added. Read the preceding
comment which I didn't change.  I left the comment but it is now inaccurate.

Signed-off-by: John David Anglin 
Signed-off-by: Helge Deller

[PARISC] fix crash in flush_icache_page_asm on PA1.1

2012-05-16T12:15:06+00:00

As pointed out by serveral people, PA1.1 only has a type 26 instruction
meaning that the space register must be explicitly encoded.  Not giving an
explicit space means that the compiler uses the type 24 version which is PA2.0
only resulting in an illegal instruction crash.

This regression was caused by

    commit f311847c2fcebd81912e2f0caf8a461dec28db41
    Author: James Bottomley 
    Date:   Wed Dec 22 10:22:11 2010 -0600

        parisc: flush pages through tmpalias space

Reported-by: Helge Deller 
Signed-off-by: John David Anglin 
Cc: stable@vger.kernel.org	#2.6.39+
Signed-off-by: James Bottomley

[PARISC] fix pacache .size with new binutils

2011-04-15T17:50:41+00:00

Fix style of flush_user_dcache_range_asm procedure declaration in
arch/parisc/kernel/pacache.s to be consistent with other assembly
procedures.

Signed-off-by: Meelis Roos 
Signed-off-by: James Bottomley

parisc: flush pages through tmpalias space

2011-01-15T14:44:40+00:00

The kernel has an 8M tmpailas space (originally designed for copying
and clearing pages but now only used for clearing).  The idea is
to place zeros into the cache above a physical page rather than into
the physical page and flush the cache, because often the zeros end up
being replaced quickly anyway.

We can also use the tmpalias space for flushing a page.  The difference
here is that we have to do tmpalias processing in the non access data and
instruction traps.  The principle is the same: as long as we know the physical
address and have a virtual address congruent to the real one, the flush will
be effective.

In order to use the tmpalias space, the icache miss path has to be enhanced to
check for the alias region to make the fic instruction effective.

Signed-off-by: James Bottomley

Revert "parisc: fix trivial section name warnings"

2008-06-13T14:49:45+00:00

This reverts commit bd3bb8c15b9a80dbddfb7905b237a4a11a4725b4.

Signed-off-by: Kyle McMartin

parisc: use conditional macro for 64-bit wide ops

2008-05-15T15:03:43+00:00

This work enables us to remove -traditional from $AFLAGS on
parisc.

Signed-off-by: Kyle McMartin

parisc: fix trivial section name warnings

2008-05-15T14:38:54+00:00

This trivial patch fixes the following section warnings on PARISC:
> WARNING: vmlinux.o (.text.1): unexpected section name.
>The (.[number]+) following section name are ld generated and not expected.
> Did you forget to use "ax"/"aw" in a .S file?
> Note that for example  contains
> section definitions for use in .S files.

Signed-off-by: Helge Deller 
Signed-off-by: Kyle McMartin