linux-toradex.git/arch/parisc/kernel/unaligned.c, branch v6.7-rc4

parisc: unaligned: Simplify 32-bit assembly in emulate_std()

2023-08-22T08:24:47+00:00

No need to extract upper and lower 32bit values of the 64-bit value. Use
gcc's %R1 to access lower 32-bits and %1 to access upper 32-bits
instead.

Signed-off-by: Helge Deller

parisc: unaligned: Include linux/sysctl.h for unaligned_enabled

2023-08-10T20:22:03+00:00

Fix sparse warning that unaligned_enabled wasn't declared.

Signed-off-by: Helge Deller

parisc: unaligned: Add required spaces after ','

2023-08-03T12:40:37+00:00

Fix checkpatch warnings:
unaligned.c:475: ERROR: space required after that ','

Signed-off-by: Yu Han 
Signed-off-by: Helge Deller

parisc: unaligned: Include header file to avoid missing prototype warnings

2023-06-30T15:14:15+00:00

Signed-off-by: Helge Deller

parisc: Fix exception handler for fldw and fstw instructions

2022-08-21T06:43:09+00:00

The exception handler is broken for unaligned memory acceses with fldw
and fstw instructions, because it trashes or uses randomly some other
floating point register than the one specified in the instruction word
on loads and stores.

The instruction "fldw 0(addr),%fr22L" (and the other fldw/fstw
instructions) encode the target register (%fr22) in the rightmost 5 bits
of the instruction word. The 7th rightmost bit of the instruction word
defines if the left or right half of %fr22 should be used.

While processing unaligned address accesses, the FR3() define is used to
extract the offset into the local floating-point register set.  But the
calculation in FR3() was buggy, so that for example instead of %fr22,
register %fr12 [((22 * 2) & 0x1f) = 12] was used.

This bug has been since forever in the parisc kernel and I wonder why it
wasn't detected earlier. Interestingly I noticed this bug just because
the libime debian package failed to build on *native* hardware, while it
successfully built in qemu.

This patch corrects the bitshift and masking calculation in FR3().

Signed-off-by: Helge Deller 
Cc:

parisc/unaligned: Fix emulate_ldw() breakage

2022-06-27T19:30:11+00:00

The commit e8aa7b17fe41 broke the 32-bit load-word unalignment exception
handler because it calculated the wrong amount of bits by which the value
should be shifted. This patch fixes it.

Signed-off-by: Helge Deller 
Fixes: e8aa7b17fe41 ("parisc/unaligned: Rewrite inline assembly of emulate_ldw()")
Cc: stable@vger.kernel.org   # v5.18

parisc/unaligned: Enhance user-space visible output

2022-03-11T18:49:31+00:00

Userspace is up to now limited to 32-bit, so it's sufficient to print
only 32-bit values when showing pointer addresses.

Signed-off-by: Helge Deller

parisc/unaligned: Rewrite 32-bit inline assembly of emulate_sth()

2022-03-11T18:49:31+00:00

Convert to use real temp variables instead of clobbering processor
registers.

Signed-off-by: Helge Deller

parisc/unaligned: Rewrite 32-bit inline assembly of emulate_ldd()

2022-03-11T18:49:31+00:00

Convert to use real temp variables instead of clobbering processor
registers.

Signed-off-by: Helge Deller

parisc/unaligned: Rewrite inline assembly of emulate_ldw()

2022-03-11T18:49:31+00:00

Convert to use real temp variables instead of clobbering processor
registers.

Signed-off-by: Helge Deller