linux-toradex.git/arch/powerpc/boot, branch tegra

powerpc/p1023rds: Fix the error of bank-width of nor flash

2011-08-31T02:27:33+00:00

In the p1023rds, a physical bus of nor flash is 16 bits width.
The bank-width is width (in bytes) of the bus width. So, the
value of bank-width of nor flash is not one, and it should be
two.

Signed-off-by: Chunhe Lan 
Signed-off-by: Kumar Gala

Merge remote-tracking branch 'jwb/next' into next

2011-07-22T03:16:41+00:00

powerpc/44x: Use correct phy-address dt nodes on taishan.dts

2011-07-12T13:35:58+00:00

Taishan (440GX) has the first PHY (EMAC2) mapped at PHY address 1
and the 2nd PHY (EMAC3) at PHY address 3. Use "phy-address" to
correctly describe this instead of "phy-map".

Signed-off-by: Stefan Roese 
Cc: Josh Boyer 
Signed-off-by: Josh Boyer

powerpc/44x: boot wrapper: allow kernel to load into non-zero address

2011-07-12T13:34:41+00:00

For AMP, different kernel instances load into separate memory regions.
Read the start of memory from the device tree and limit the memory to what's
specified in the device tree.

Signed-off-by: Dave Kleikamp 
Signed-off-by: Tony Breeds 
Cc: Benjamin Herrenschmidt 
Cc: Josh Boyer 
Cc: linuxppc-dev@lists.ozlabs.org
Signed-off-by: Josh Boyer

powerpc/p1022ds: Remove fixed-link property from ethernet nodes.

2011-07-08T05:21:34+00:00

On P1022DS both ethernet controllers are connected to RGMII PHYs
accessible via MDIO bus. Remove fixed-link property from ethernet
nodes as they only required when fixed link PHYs without MDIO bus
are used.

Signed-off-by: Felix Radensky 
Acked-by: Timur Tabi 
Signed-off-by: Kumar Gala

powerpc/85xx: Add p2040 RDB board support

2011-07-08T05:21:32+00:00

P2040RDB Specification:
-----------------------
2Gbyte unbuffered DDR3 SDRAM SO-DIMM(64bit bus)
128 Mbyte NOR flash single-chip memory
256 Kbit M24256 I2C EEPROM
16 Mbyte SPI memory
SD connector to interface with the SD memory card
dTSEC1: connected to the Vitesse SGMII PHY (VSC8221)
dTSEC2: connected to the Vitesse SGMII PHY (VSC8221)
dTSEC3: connected to the Vitesse SGMII PHY (VSC8221)
dTSEC4: connected to the Vitesse RGMII PHY (VSC8641)
dTSEC5: connected to the Vitesse RGMII PHY (VSC8641)
I2C1: Real time clock, Temperature sensor
I2C2: Vcore Regulator, 256Kbit I2C Bus EEPROM
SATA: Lanes C and Land D of Bank2 are connected to two SATA connectors
UART: supports two UARTs up to 115200 bps for console
USB 2.0: connected via a internal UTMI PHY to two TYPE-A interfaces
PCIe:
 - Lanes E, F, G and H of Bank1 are connected to one x4 PCIe SLOT1
 - Lanes C and Land D of Bank2 are connected to one x4 PCIe SLOT2

Signed-off-by: Mingkai Hu 
Signed-off-by: Kumar Gala

powerpc/85xx: Add P5020 SoC device tree include stub

2011-07-07T14:33:50+00:00

Split out common (non-board specific) parts of the SoC related device
tree into a stub so multiple board dts files can include it and we can
reduce duplication and maintenance effort.

Signed-off-by: Kumar Gala

powerpc/85xx: Add P3041 SoC device tree include stub

2011-07-07T14:33:50+00:00

Split out common (non-board specific) parts of the SoC related device
tree into a stub so multiple board dts files can include it and we can
reduce duplication and maintenance effort.

Signed-off-by: Kumar Gala

Merge remote branch 'origin/master' into next

2011-06-30T05:23:59+00:00

Merge remote branch 'jwb/next' into next

2011-06-29T02:45:43+00:00