linux-toradex.git/arch/powerpc/include/asm/mmu.h, branch v3.7.4

powerpc/mm: Make some of the PGTABLE_RANGE dependency explicit

2012-09-17T06:31:53+00:00

slice array size and slice mask size depend on PGTABLE_RANGE.

Reviewed-by: Paul Mackerras 
Signed-off-by: Aneesh Kumar K.V 
Signed-off-by: Benjamin Herrenschmidt

powerpc/mm: remove obsolete comment about page size name array

2012-07-03T04:14:50+00:00

The array of names in hugetlbpage.c no longer exists.

Signed-off-by: Scott Wood 
Signed-off-by: Benjamin Herrenschmidt

powerpc: Hugetlb for BookE

2011-09-19T23:19:40+00:00

Enable hugepages on Freescale BookE processors.  This allows the kernel to
use huge TLB entries to map pages, which can greatly reduce the number of
TLB misses and the amount of TLB thrashing experienced by applications with
large memory footprints.  Care should be taken when using this on FSL
processors, as the number of large TLB entries supported by the core is low
(16-64) on current processors.

The supported set of hugepage sizes include 4m, 16m, 64m, 256m, and 1g.
Page sizes larger than the max zone size are called "gigantic" pages and
must be allocated on the command line (and cannot be deallocated).

This is currently only fully implemented for Freescale 32-bit BookE
processors, but there is some infrastructure in the code for
64-bit BooKE.

Signed-off-by: Becky Bruce 
Signed-off-by: David Gibson 
Signed-off-by: Benjamin Herrenschmidt

Merge remote-tracking branch 'jwb/next' into next

2011-07-22T03:16:41+00:00

powerpc/44x: don't use tlbivax on AMP systems

2011-07-12T13:21:55+00:00

Since other OS's may be running on the other cores don't use tlbivax

Signed-off-by: Dave Kleikamp 
Signed-off-by: Tony Breeds 
Cc: Benjamin Herrenschmidt 
Cc: Josh Boyer 
Cc: linuxppc-dev@lists.ozlabs.org
Signed-off-by: Josh Boyer

powerpc: Create next_tlbcam_idx percpu variable for FSL_BOOKE

2011-07-08T05:21:34+00:00

This is used to round-robin TLBCAM entries.

Signed-off-by: Becky Bruce 
Signed-off-by: Kumar Gala

powerpc: Use new CPU feature bit to select 2.06 tlbie

2011-05-04T05:19:26+00:00

This removes MMU_FTR_TLBIE_206 as we can now use CPU_FTR_HVMODE_206.  It
also changes the logic to select which tlbie to use to be based on this
new CPU feature bit.

This also duplicates the ASM_FTR_IF/SET/CLR defines for CPU features
(copied from MMU features).

Signed-off-by: Michael Neuling 
Signed-off-by: Benjamin Herrenschmidt

powerpc: Free up some CPU feature bits by moving out MMU-related features

2011-04-27T04:18:52+00:00

Some of the 64bit PPC CPU features are MMU-related, so this patch moves
them to MMU_FTR_ bits.  All cpu_has_feature()-style tests are moved to
mmu_has_feature(), and seven feature bits are freed as a result.

Signed-off-by: Matt Evans 
Signed-off-by: Benjamin Herrenschmidt

memblock: Remove rmo_size, burry it in arch/powerpc where it belongs

2010-08-05T02:56:08+00:00

The RMA (RMO is a misnomer) is a concept specific to ppc64 (in fact
server ppc64 though I hijack it on embedded ppc64 for similar purposes)
and represents the area of memory that can be accessed in real mode
(aka with MMU off), or on embedded, from the exception vectors (which
is bolted in the TLB) which pretty much boils down to the same thing.

We take that out of the generic MEMBLOCK data structure and move it into
arch/powerpc where it belongs, renaming it to "RMA" while at it.

Signed-off-by: Benjamin Herrenschmidt

powerpc/47x: Base ppc476 support

2010-05-05T13:11:10+00:00

This patch adds the base support for the 476 processor.  The code was
primarily written by Ben Herrenschmidt and Torez Smith, but I've been
maintaining it for a while.

The goal is to have a single binary that will run on 44x and 47x, but
we still have some details to work out.  The biggest is that the L1 cache
line size differs on the two platforms, but it's currently a compile-time
option.

Signed-off-by: Benjamin Herrenschmidt 
Signed-off-by: Torez Smith  
Signed-off-by: Dave Kleikamp 
Signed-off-by: Josh Boyer