linux-toradex.git/arch/powerpc/include/asm/tlbflush.h, branch v3.17

powerpc/THP: Implement transparent hugepages for ppc64

2013-06-21T06:01:53+00:00

We now have pmd entries covering 16MB range and the PMD table double its original size.
We use the second half of the PMD table to deposit the pgtable (PTE page).
The depoisted PTE page is further used to track the HPTE information. The information
include [ secondary group | 3 bit hidx | valid ]. We use one byte per each HPTE entry.
With 16MB hugepage and 64K HPTE we need 256 entries and with 4K HPTE we need
4096 entries. Both will fit in a 4K PTE page. On hugepage invalidate we need to walk
the PTE page and invalidate all valid HPTEs.

This patch implements necessary arch specific functions for THP support and also
hugepage invalidate logic. These PMD related functions are intentionally kept
similar to their PTE counter-part.

Signed-off-by: Aneesh Kumar K.V 
Signed-off-by: Benjamin Herrenschmidt

powerpc/mm: Make some of the PGTABLE_RANGE dependency explicit

2012-09-17T06:31:53+00:00

slice array size and slice mask size depend on PGTABLE_RANGE.

Reviewed-by: Paul Mackerras 
Signed-off-by: Aneesh Kumar K.V 
Signed-off-by: Benjamin Herrenschmidt

powerpc/mm: Convert virtual address to vpn

2012-09-17T06:31:49+00:00

This patch convert different functions to take virtual page number
instead of virtual address. Virtual page number is virtual address
shifted right by VPN_SHIFT (12) bits. This enable us to have an
address range of upto 76 bits.

Reviewed-by: Paul Mackerras 
Signed-off-by: Aneesh Kumar K.V 
Signed-off-by: Benjamin Herrenschmidt

powerpc/mm: Standardise on MMU_NO_CONTEXT

2011-04-20T06:59:20+00:00

Use MMU_NO_CONTEXT as the initialiser for mm_context.id on
nohash and hash64.

Signed-off-by: Michael Ellerman 
Signed-off-by: Benjamin Herrenschmidt

powerpc/mm: Make low level TLB flush ops on BookE take additional args

2009-08-20T00:12:41+00:00

We need to pass down whether the page is direct or indirect and we'll
need to pass the page size to _tlbil_va and _tlbivax_bcast

We also add a new low level _tlbil_pid_noind() which does a TLB flush
by PID but avoids flushing indirect entries if possible

This implements those new prototypes but defines them with inlines
or macros so that no additional arguments are actually passed on current
processors.

Signed-off-by: Benjamin Herrenschmidt

powerpc/mm: Split low level tlb invalidate for nohash processors

2008-12-21T03:21:16+00:00

Currently, the various forms of low level TLB invalidations are all
implemented in misc_32.S for 32-bit processors, in a fairly scary
mess of #ifdef's and with interesting duplication such as a whole
bunch of code for FSL _tlbie and _tlbia which are no longer used.

This moves things around such that _tlbie is now defined in
hash_low_32.S and is only used by the 32-bit hash code, and all
nohash CPUs use the various _tlbil_* forms that are now moved to
a new file, tlb_nohash_low.S.

I moved all the definitions for that stuff out of
include/asm/tlbflush.h as they are really internal mm stuff, into
mm/mmu_decl.h

The code should have no functional changes.  I kept some variants
inline for trivial forms on things like 40x and 8xx.

Signed-off-by: Benjamin Herrenschmidt 
Acked-by: Kumar Gala 
Signed-off-by: Paul Mackerras

powerpc/mm: Add SMP support to no-hash TLB handling

2008-12-21T03:21:16+00:00

This commit moves the whole no-hash TLB handling out of line into a
new tlb_nohash.c file, and implements some basic SMP support using
IPIs and/or broadcast tlbivax instructions.

Note that I'm using local invalidations for D->I cache coherency.

At worst, if another processor is trying to execute the same and
has the old entry in its TLB, it will just take a fault and re-do
the TLB flush locally (it won't re-do the cache flush in any case).

Signed-off-by: Benjamin Herrenschmidt 
Acked-by: Kumar Gala 
Signed-off-by: Paul Mackerras

powerpc/mm: Rework context management for CPUs with no hash table

2008-12-21T03:21:15+00:00

This reworks the context management code used by 4xx,8xx and
freescale BookE.  It adds support for SMP by implementing a
concept of stale context map to lazily flush the TLB on
processors where a context may have been invalidated.  This
also contains the ground work for generalizing such lazy TLB
flushing by just picking up a new PID and marking the old one
stale.  This will be implemented later.

This is a first implementation that uses a global spinlock.

Ideally, we should try to get at least the fast path (context ID
already assigned) lockless or limited to a per context lock,
but for now this will do.

I tried to keep the UP case reasonably simple to avoid adding
too much overhead to 8xx which does a lot of context stealing
since it effectively has only 16 PIDs available.

Signed-off-by: Benjamin Herrenschmidt 
Acked-by: Kumar Gala 
Signed-off-by: Paul Mackerras

powerpc/mm: Add local_flush_tlb_mm() to SW loaded TLB implementations

2008-12-16T04:53:26+00:00

This adds a local_flush_tlb_mm() call as a pre-requisite for some
SMP work for BookE processors.

Signed-off-by: Benjamin Herrenschmidt 
Acked-by: Kumar Gala 
Signed-off-by: Paul Mackerras

powerpc: Add a local_flush_tlb_page to handle kmap_atomic invalidates

2008-12-03T09:46:35+00:00

The tlb invalidates in kmap_atomic/kunmap_atomic can be called from
IRQ context, however they are only local invalidates (on the processor
that the kmap was called on).  In the future we want to use IPIs to
do tlb invalidates this causes issue since flush_tlb_page() is considered
a broadcast invalidate.

Add local_flush_tlb_page() as a non-broadcast invalidate and use it in
kmap_atomic() since we don't have enough information in the
flush_tlb_page() call to determine its local.

Signed-off-by: Kumar Gala 
Acked-by: Benjamin Herrenschmidt 
Signed-off-by: Paul Mackerras