<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-toradex.git/arch/powerpc/kernel/cpu_setup_44x.S, branch v3.3.5</title>
<subtitle>Linux kernel for Apalis and Colibri modules</subtitle>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/'/>
<entry>
<title>powerpc/44x: Add support for the AMCC APM821xx SoC</title>
<updated>2010-10-13T12:47:09+00:00</updated>
<author>
<name>Tirumala Marri</name>
<email>tmarri@apm.com</email>
</author>
<published>2010-09-13T13:26:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=6edc323db720c65b9e6a770b4bed98f251dd49f0'/>
<id>6edc323db720c65b9e6a770b4bed98f251dd49f0</id>
<content type='text'>
This patch adds CPU, device tree, defconfig and bluestone board
support for APM821xx SoC.

Signed-off-by: Tirumala R Marri &lt;tmarri@apm.com&gt;
Signed-off-by: Josh Boyer &lt;jwboyer@linux.vnet.ibm.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch adds CPU, device tree, defconfig and bluestone board
support for APM821xx SoC.

Signed-off-by: Tirumala R Marri &lt;tmarri@apm.com&gt;
Signed-off-by: Josh Boyer &lt;jwboyer@linux.vnet.ibm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>AMCC PPC 460SX redwood SoC platform initial framework</title>
<updated>2009-02-14T19:41:29+00:00</updated>
<author>
<name>Madhulika Madishetty</name>
<email>mmadishetty@amcc.com</email>
</author>
<published>2009-02-05T13:31:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=6c7120902305b3a21460cd2f0f917a39307df566'/>
<id>6c7120902305b3a21460cd2f0f917a39307df566</id>
<content type='text'>
This patch contains initial framework for the AMCC Redwood board.

Signed-off-by: Madhulika Madishetty &lt;mmadishetty@amcc.com&gt;
Signed-off-by: Tirumala Marri &lt;tmarri@amcc.com&gt;
Signed-off-by: Feng Kan &lt;fkan@amcc.com&gt;
Signed-off-by: Vidhyananth Venkatasamy &lt;vvenkatasamy@amcc.com&gt;
Signed-off-by: Preetesh Parekh &lt;pparekh@amcc.com&gt;
Acked-by: Loc Ho &lt;lho@amcc.com&gt;
Acked-by: Feng Kan &lt;fkan@amcc.com&gt;
Signed-off-by: Josh Boyer &lt;jwboyer@linux.vnet.ibm.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch contains initial framework for the AMCC Redwood board.

Signed-off-by: Madhulika Madishetty &lt;mmadishetty@amcc.com&gt;
Signed-off-by: Tirumala Marri &lt;tmarri@amcc.com&gt;
Signed-off-by: Feng Kan &lt;fkan@amcc.com&gt;
Signed-off-by: Vidhyananth Venkatasamy &lt;vvenkatasamy@amcc.com&gt;
Signed-off-by: Preetesh Parekh &lt;pparekh@amcc.com&gt;
Acked-by: Loc Ho &lt;lho@amcc.com&gt;
Acked-by: Feng Kan &lt;fkan@amcc.com&gt;
Signed-off-by: Josh Boyer &lt;jwboyer@linux.vnet.ibm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/virtex5: Fix Virtex5 machine check handling</title>
<updated>2008-12-05T19:34:26+00:00</updated>
<author>
<name>Grant Likely</name>
<email>grant.likely@secretlab.ca</email>
</author>
<published>2008-12-04T05:39:55+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=640d17d60e83401e10e66a0ab6e9e2d6350df656'/>
<id>640d17d60e83401e10e66a0ab6e9e2d6350df656</id>
<content type='text'>
The 440x5 core in the Virtex5 uses the 440A type machine check
(ie, they have MCSRR0/MCSRR1). They thus need to call the
appropriate fixup function to hook the right variant of the
exception.

Without this, all machine checks become fatal due to loss
of context when entering the exception handler.

Signed-off-by: Grant Likely &lt;grant.likely@secretlab.ca&gt;
Signed-off-by: Josh Boyer &lt;jwboyer@linux.vnet.ibm.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The 440x5 core in the Virtex5 uses the 440A type machine check
(ie, they have MCSRR0/MCSRR1). They thus need to call the
appropriate fixup function to hook the right variant of the
exception.

Without this, all machine checks become fatal due to loss
of context when entering the exception handler.

Signed-off-by: Grant Likely &lt;grant.likely@secretlab.ca&gt;
Signed-off-by: Josh Boyer &lt;jwboyer@linux.vnet.ibm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/44x: Fix 460EX/460GT machine check handling</title>
<updated>2008-11-13T15:11:26+00:00</updated>
<author>
<name>Benjamin Herrenschmidt</name>
<email>benh@kernel.crashing.org</email>
</author>
<published>2008-11-11T16:02:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=6612d9b0b8208c2ade3a16b8302a271ec81d45f6'/>
<id>6612d9b0b8208c2ade3a16b8302a271ec81d45f6</id>
<content type='text'>
Those cores use the 440A type machine check (ie, they have
MCSRR0/MCSRR1). They thus need to call the appropriate fixup
function to hook the right variant of the exception.

Without this, all machine checks become fatal due to loss
of context when entering the exception handler.

Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
Signed-off-by: Josh Boyer &lt;jwboyer@linux.vnet.ibm.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Those cores use the 440A type machine check (ie, they have
MCSRR0/MCSRR1). They thus need to call the appropriate fixup
function to hook the right variant of the exception.

Without this, all machine checks become fatal due to loss
of context when entering the exception handler.

Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
Signed-off-by: Josh Boyer &lt;jwboyer@linux.vnet.ibm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc: Remove use of CONFIG_PPC_MERGE</title>
<updated>2008-08-04T03:18:17+00:00</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2008-08-01T16:44:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=9c4cb82515130c62224e23fdf7c13c8f6c59c614'/>
<id>9c4cb82515130c62224e23fdf7c13c8f6c59c614</id>
<content type='text'>
Now that arch/ppc is gone and CONFIG_PPC_MERGE is always set, remove
the dead code associated with !CONFIG_PPC_MERGE from arch/powerpc
and include/asm-powerpc.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
Signed-off-by: Paul Mackerras &lt;paulus@samba.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Now that arch/ppc is gone and CONFIG_PPC_MERGE is always set, remove
the dead code associated with !CONFIG_PPC_MERGE from arch/powerpc
and include/asm-powerpc.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
Signed-off-by: Paul Mackerras &lt;paulus@samba.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Revert "[POWERPC] 4xx: Fix 460GT support to not enable FPU"</title>
<updated>2008-06-11T11:52:40+00:00</updated>
<author>
<name>Josh Boyer</name>
<email>jwboyer@linux.vnet.ibm.com</email>
</author>
<published>2008-06-11T11:52:40+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=939e622c5e7f8ccd6b0a05a810114b368f7de69e'/>
<id>939e622c5e7f8ccd6b0a05a810114b368f7de69e</id>
<content type='text'>
This reverts commit acb0142bf01c0ebe18f09e37814451ee6a873e27.

AMCC has indicated that the PPC 460GT does have FPU support.  This
revert enables the FPU for those chips again.

Signed-off-by: Josh Boyer &lt;jwboyer@linux.vnet.ibm.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This reverts commit acb0142bf01c0ebe18f09e37814451ee6a873e27.

AMCC has indicated that the PPC 460GT does have FPU support.  This
revert enables the FPU for those chips again.

Signed-off-by: Josh Boyer &lt;jwboyer@linux.vnet.ibm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[POWERPC] 4xx: Fix 460GT support to not enable FPU</title>
<updated>2008-04-24T18:32:47+00:00</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2008-04-19T09:57:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=acb0142bf01c0ebe18f09e37814451ee6a873e27'/>
<id>acb0142bf01c0ebe18f09e37814451ee6a873e27</id>
<content type='text'>
The AMCC 460GT doesn't have an FPU so let's not enable support for it.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Signed-off-by: Josh Boyer &lt;jwboyer@linux.vnet.ibm.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The AMCC 460GT doesn't have an FPU so let's not enable support for it.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Signed-off-by: Josh Boyer &lt;jwboyer@linux.vnet.ibm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[POWERPC] 4xx: Add AMCC 460EX/460GT support to cputable.c &amp; cpu_setup_44x.S</title>
<updated>2008-03-26T12:19:16+00:00</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2008-02-23T21:07:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=464076a4b328946528998513c4ef799fd60de588'/>
<id>464076a4b328946528998513c4ef799fd60de588</id>
<content type='text'>
This patch adds basic support for the AMCC 460EX/460GT PPC's to arch/powerpc.
Currently those PPC's are still based on a 440 core and *not* a 460 core.

Here some basic features of those SoC's:

460EX:
- Up to 1.2GHz, 32kB L1 I-cache and D-cache, 256kB L2-cache, FPU
- 1 * PCI (max 66MHz), 2 * PCIe (one 4-lane, one 1-lane)
- 2 * GBit Ethernet with TCP/IP acceleration
- USB 2.0 Host/Device OTG and Host interface
- SATA controller
- Optional security feature

460GT (only changes to 460EX):
- 4 * GBit Ethernet with TCP/IP acceleration
- RapidIO
- No SATA
- No USB

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Signed-off-by: Josh Boyer &lt;jwboyer@linux.vnet.ibm.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch adds basic support for the AMCC 460EX/460GT PPC's to arch/powerpc.
Currently those PPC's are still based on a 440 core and *not* a 460 core.

Here some basic features of those SoC's:

460EX:
- Up to 1.2GHz, 32kB L1 I-cache and D-cache, 256kB L2-cache, FPU
- 1 * PCI (max 66MHz), 2 * PCIe (one 4-lane, one 1-lane)
- 2 * GBit Ethernet with TCP/IP acceleration
- USB 2.0 Host/Device OTG and Host interface
- SATA controller
- Optional security feature

460GT (only changes to 460EX):
- 4 * GBit Ethernet with TCP/IP acceleration
- RapidIO
- No SATA
- No USB

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Signed-off-by: Josh Boyer &lt;jwboyer@linux.vnet.ibm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[POWERPC] 4xx: Fix 440grx setup function to call 440A fixup</title>
<updated>2007-12-23T19:27:37+00:00</updated>
<author>
<name>Josh Boyer</name>
<email>jwboyer@linux.vnet.ibm.com</email>
</author>
<published>2007-12-04T19:02:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=9ac30c314529af21ae739375d25c7da78887363b'/>
<id>9ac30c314529af21ae739375d25c7da78887363b</id>
<content type='text'>
The mechanism to do the setup for 440A cores changed recently.  This fixes
the 440grx setup function to call __fixup_440A_mcheck.

Signed-off-by: Josh Boyer &lt;jwboyer@linux.vnet.ibm.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The mechanism to do the setup for 440A cores changed recently.  This fixes
the 440grx setup function to call __fixup_440A_mcheck.

Signed-off-by: Josh Boyer &lt;jwboyer@linux.vnet.ibm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[POWERPC] Reworking machine check handling and Fix 440/440A</title>
<updated>2007-12-23T19:11:59+00:00</updated>
<author>
<name>Benjamin Herrenschmidt</name>
<email>benh@kernel.crashing.org</email>
</author>
<published>2007-12-21T04:39:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=47c0bd1ae24c34e851cf0f2b02ef2a6847d7ae15'/>
<id>47c0bd1ae24c34e851cf0f2b02ef2a6847d7ae15</id>
<content type='text'>
This adds a cputable function pointer for the CPU-side machine
check handling. The semantic is still the same as the old one,
the one in ppc_md. overrides the one in cputable, though
ultimately we'll want to change that so the CPU gets first.

This removes CONFIG_440A which was a problem for multiplatform
kernels and instead fixes up the IVOR at runtime from a setup_cpu
function. The "A" version of the machine check also tweaks the
regs-&gt;trap value to differenciate the 2 versions at the C level.

Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
Signed-off-by: Josh Boyer &lt;jwboyer@linux.vnet.ibm.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This adds a cputable function pointer for the CPU-side machine
check handling. The semantic is still the same as the old one,
the one in ppc_md. overrides the one in cputable, though
ultimately we'll want to change that so the CPU gets first.

This removes CONFIG_440A which was a problem for multiplatform
kernels and instead fixes up the IVOR at runtime from a setup_cpu
function. The "A" version of the machine check also tweaks the
regs-&gt;trap value to differenciate the 2 versions at the C level.

Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
Signed-off-by: Josh Boyer &lt;jwboyer@linux.vnet.ibm.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
