linux-toradex.git/arch/powerpc/kernel/cpu_setup_6xx.S, branch v6.4-rc2

powerpc/32: Fix objtool unannotated intra-function call warnings

2022-11-18T08:00:06+00:00

Fix several annotations in assembly files on PPC32.

[Sathvika Vasireddy: Changed subject line and removed Kconfig change to
 enable objtool, as it is a part of "objtool/powerpc: Enable objtool to
 be built on ppc" patch in this series.]

Tested-by: Naveen N. Rao 
Reviewed-by: Naveen N. Rao 
Acked-by: Josh Poimboeuf 
Signed-off-by: Christophe Leroy 
Signed-off-by: Sathvika Vasireddy 
Signed-off-by: Michael Ellerman 
Link: https://lore.kernel.org/r/20221114175754.1131267-7-sv@linux.ibm.com

powerpc/32: Blacklist functions running with MMU disabled for kprobe

2020-06-02T10:59:11+00:00

kprobe does not handle events happening in real mode, all
functions running with MMU disabled have to be blacklisted.

Signed-off-by: Christophe Leroy 
Acked-by: Naveen N. Rao 
Signed-off-by: Michael Ellerman 
Link: https://lore.kernel.org/r/3bf57066d05518644dee0840af69d36ab5086729.1585670437.git.christophe.leroy@c-s.fr

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152

2019-05-30T18:26:32+00:00

Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license as published by
  the free software foundation either version 2 of the license or at
  your option any later version

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-or-later

has been chosen to replace the boilerplate/reference in 3029 file(s).

Signed-off-by: Thomas Gleixner 
Reviewed-by: Allison Randal 
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de
Signed-off-by: Greg Kroah-Hartman

powerpc/6xx: fix setup and use of SPRN_SPRG_PGDIR for hash32

2019-03-18T13:30:19+00:00

Not only the 603 but all 6xx need SPRN_SPRG_PGDIR to be initialised at
startup. This patch move it from __setup_cpu_603() to start_here()
and __secondary_start(), close to the initialisation of SPRN_THREAD.

Previously, virt addr of PGDIR was retrieved from thread struct.
Now that it is the phys addr which is stored in SPRN_SPRG_PGDIR,
hash_page() shall not convert it to phys anymore.
This patch removes the conversion.

Fixes: 93c4a162b014 ("powerpc/6xx: Store PGDIR physical address in a SPRG")
Reported-by: Guenter Roeck 
Tested-by: Guenter Roeck 
Signed-off-by: Christophe Leroy 
Signed-off-by: Michael Ellerman

powerpc/6xx: Store PGDIR physical address in a SPRG

2019-02-21T13:10:16+00:00

Use SPRN_SPRG2 to store the current thread PGDIR and
avoid reading thread_struct.pgdir at every TLB miss.

Signed-off-by: Christophe Leroy 
Signed-off-by: Michael Ellerman

powerpc: change CONFIG_6xx to CONFIG_PPC_BOOK3S_32

2018-11-26T11:33:37+00:00

Today we have:

config PPC_BOOK3S_32
	bool "512x/52xx/6xx/7xx/74xx/82xx/83xx/86xx"
	[depends on PPC32 within a choice]

config PPC_BOOK3S
	def_bool y
	depends on PPC_BOOK3S_32 || PPC_BOOK3S_64

config 6xx
	def_bool y
	depends on PPC32 && PPC_BOOK3S

6xx is therefore redundant with PPC_BOOK3S_32.

In order to make the code clearer, lets use preferably PPC_BOOK3S_32.
This will allow to remove CONFIG_6xx in a later patch.

Signed-off-by: Christophe Leroy 
Signed-off-by: Michael Ellerman

powerpc: clean inclusions of asm/feature-fixups.h

2018-07-30T12:48:17+00:00

files not using feature fixup don't need asm/feature-fixups.h
files using feature fixup need asm/feature-fixups.h

Signed-off-by: Christophe Leroy 
Signed-off-by: Michael Ellerman

powerpc: Free up CPU feature bits on 64-bit machines

2018-03-23T13:38:51+00:00

This moves all the CPU feature bits that are only used on 32-bit
machines to the top 20 bits of the CPU feature word and arranges
for them to be defined only in 32-bit builds.  The features that
are common to 32-bit and 64-bit machines are moved to bits 0-11
of the CPU feature word.  This means that for 64-bit platforms,
bits 44-63 can now be used for new features that only exist on
64-bit machines.  (These bit numbers are counting from the right,
i.e. the LSB is bit 0.)

Because CPU_FTR_L3_DISABLE_NAP moved from the low 16 bits to the high
16 bits, we have to adjust some assembly code.  Also, CPU_FTR_EMB_HV
moved from the high 16 bits to the low 16 bits.

Note that CPU_FTR_REAL_LE only applies to 64-bit chips, because only
64-bit chips (POWER6, 7, 8, 9) have a true little-endian mode that is
a CPU execution mode as opposed to being a page attribute.

With this we now have 20 free CPU feature bits on 64-bit machines.

Signed-off-by: Paul Mackerras 
Signed-off-by: Michael Ellerman

powerpc: Various typo fixes

2016-06-14T03:58:26+00:00

Signed-off-by: Andrea Gelmini 
Signed-off-by: Michael Ellerman

powerpc: Fix some 6xx/7xxx CPU setup functions

2011-02-07T01:57:11+00:00

Some of those functions try to adjust the CPU features, for example
to remove NAP support on some revisions. However, they seem to use
r5 as an index into the CPU table entry, which might have been right
a long time ago but no longer is. r4 is the right register to use.

This probably caused some off behaviours on some PowerMac variants
using 750cx or 7455 processor revisions.

Signed-off-by: Benjamin Herrenschmidt 
CC: stable@kernel.org