<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-toradex.git/arch/powerpc/kernel/cpu_setup_fsl_booke.S, branch v4.3-rc2</title>
<subtitle>Linux kernel for Apalis and Colibri modules</subtitle>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/'/>
<entry>
<title>powerpc/booke: Restrict SPE exception handlers to e200/e500 cores</title>
<updated>2014-09-22T08:11:31+00:00</updated>
<author>
<name>Mihai Caraman</name>
<email>mihai.caraman@freescale.com</email>
</author>
<published>2014-08-20T13:09:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=3477e71d53197d7f1b6a1f7416f3c42ffec5f221'/>
<id>3477e71d53197d7f1b6a1f7416f3c42ffec5f221</id>
<content type='text'>
SPE exception handlers are now defined for 32-bit e500mc cores even though
SPE unit is not present and CONFIG_SPE is undefined.

Restrict SPE exception handlers to e200/e500 cores adding CONFIG_SPE_POSSIBLE
and consequently guard __stup_ivors and __setup_cpu functions.

Signed-off-by: Mihai Caraman &lt;mihai.caraman@freescale.com&gt;
Acked-by: Scott Wood &lt;scottwood@freescale.com&gt;
Signed-off-by: Alexander Graf &lt;agraf@suse.de&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
SPE exception handlers are now defined for 32-bit e500mc cores even though
SPE unit is not present and CONFIG_SPE is undefined.

Restrict SPE exception handlers to e200/e500 cores adding CONFIG_SPE_POSSIBLE
and consequently guard __stup_ivors and __setup_cpu functions.

Signed-off-by: Mihai Caraman &lt;mihai.caraman@freescale.com&gt;
Acked-by: Scott Wood &lt;scottwood@freescale.com&gt;
Signed-off-by: Alexander Graf &lt;agraf@suse.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc: No need to use dot symbols when branching to a function</title>
<updated>2014-04-23T00:05:16+00:00</updated>
<author>
<name>Anton Blanchard</name>
<email>anton@samba.org</email>
</author>
<published>2014-02-04T05:04:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=b1576fec7f4dd4657694fefc97fda4cf28ec68e9'/>
<id>b1576fec7f4dd4657694fefc97fda4cf28ec68e9</id>
<content type='text'>
binutils is smart enough to know that a branch to a function
descriptor is actually a branch to the functions text address.

Alan tells me that binutils has been doing this for 9 years.

Signed-off-by: Anton Blanchard &lt;anton@samba.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
binutils is smart enough to know that a branch to a function
descriptor is actually a branch to the functions text address.

Alan tells me that binutils has been doing this for 9 years.

Signed-off-by: Anton Blanchard &lt;anton@samba.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/85xx: add hardware automatically enter pw20 state</title>
<updated>2014-01-08T01:40:28+00:00</updated>
<author>
<name>Wang Dongsheng</name>
<email>dongsheng.wang@freescale.com</email>
</author>
<published>2013-12-17T08:17:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=1d47ddf7c3725e889763b1fffa70a04e1061940b'/>
<id>1d47ddf7c3725e889763b1fffa70a04e1061940b</id>
<content type='text'>
Using hardware features make core automatically enter PW20 state.
Set a TB count to hardware, the effective count begins when PW10
is entered. When the effective period has expired, the core will
proceed from PW10 to PW20 if no exit conditions have occurred during
the period.

Signed-off-by: Wang Dongsheng &lt;dongsheng.wang@freescale.com&gt;
Signed-off-by: Scott Wood &lt;scottwood@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Using hardware features make core automatically enter PW20 state.
Set a TB count to hardware, the effective count begins when PW10
is entered. When the effective period has expired, the core will
proceed from PW10 to PW20 if no exit conditions have occurred during
the period.

Signed-off-by: Wang Dongsheng &lt;dongsheng.wang@freescale.com&gt;
Signed-off-by: Scott Wood &lt;scottwood@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/85xx: add hardware automatically enter altivec idle state</title>
<updated>2014-01-08T01:39:48+00:00</updated>
<author>
<name>Wang Dongsheng</name>
<email>dongsheng.wang@freescale.com</email>
</author>
<published>2013-12-17T08:17:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=202e059ce34d5c5e3ff8a542866c280d575ccb17'/>
<id>202e059ce34d5c5e3ff8a542866c280d575ccb17</id>
<content type='text'>
Each core's AltiVec unit may be placed into a power savings mode
by turning off power to the unit. Core hardware will automatically
power down the AltiVec unit after no AltiVec instructions have
executed in N cycles. The AltiVec power-control is triggered by hardware.

Signed-off-by: Wang Dongsheng &lt;dongsheng.wang@freescale.com&gt;
Signed-off-by: Scott Wood &lt;scottwood@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Each core's AltiVec unit may be placed into a power savings mode
by turning off power to the unit. Core hardware will automatically
power down the AltiVec unit after no AltiVec instructions have
executed in N cycles. The AltiVec power-control is triggered by hardware.

Signed-off-by: Wang Dongsheng &lt;dongsheng.wang@freescale.com&gt;
Signed-off-by: Scott Wood &lt;scottwood@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/booke64: Add LRAT error exception handler</title>
<updated>2014-01-08T00:15:29+00:00</updated>
<author>
<name>Mihai Caraman</name>
<email>mihai.caraman@freescale.com</email>
</author>
<published>2013-08-08T12:56:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=228b1a473037c89d524e03a569c688a22241b4ea'/>
<id>228b1a473037c89d524e03a569c688a22241b4ea</id>
<content type='text'>
LRAT (Logical to Real Address Translation) present in MMU v2 provides hardware
translation from a logical page number (LPN) to a real page number (RPN) when
tlbwe is executed by a guest or when a page table translation occurs from a
guest virtual address.

Add LRAT error exception handler to Booke3E 64-bit kernel and the basic KVM
handler to avoid build breakage. This is a prerequisite for KVM LRAT support
that will follow.

Signed-off-by: Mihai Caraman &lt;mihai.caraman@freescale.com&gt;
Signed-off-by: Scott Wood &lt;scottwood@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
LRAT (Logical to Real Address Translation) present in MMU v2 provides hardware
translation from a logical page number (LPN) to a real page number (RPN) when
tlbwe is executed by a guest or when a page table translation occurs from a
guest virtual address.

Add LRAT error exception handler to Booke3E 64-bit kernel and the basic KVM
handler to avoid build breakage. This is a prerequisite for KVM LRAT support
that will follow.

Signed-off-by: Mihai Caraman &lt;mihai.caraman@freescale.com&gt;
Signed-off-by: Scott Wood &lt;scottwood@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx</title>
<updated>2013-07-30T20:50:07+00:00</updated>
<author>
<name>Hongtao Jia</name>
<email>hongtao.jia@freescale.com</email>
</author>
<published>2013-04-28T05:20:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=4e0e3435b50285eafe5898124ce02f7577f6803a'/>
<id>4e0e3435b50285eafe5898124ce02f7577f6803a</id>
<content type='text'>
A PCIe erratum of mpc85xx may causes a core hang when a link of PCIe
goes down. when the link goes down, Non-posted transactions issued
via the ATMU requiring completion result in an instruction stall.
At the same time a machine-check exception is generated to the core
to allow further processing by the handler. We implements the handler
which skips the instruction caused the stall.

This patch depends on patch:
powerpc/85xx: Add platform_device declaration to fsl_pci.h

Signed-off-by: Zhao Chenhui &lt;b35336@freescale.com&gt;
Signed-off-by: Li Yang &lt;leoli@freescale.com&gt;
Signed-off-by: Liu Shuo &lt;soniccat.liu@gmail.com&gt;
Signed-off-by: Jia Hongtao &lt;hongtao.jia@freescale.com&gt;
Signed-off-by: Scott Wood &lt;scottwood@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
A PCIe erratum of mpc85xx may causes a core hang when a link of PCIe
goes down. when the link goes down, Non-posted transactions issued
via the ATMU requiring completion result in an instruction stall.
At the same time a machine-check exception is generated to the core
to allow further processing by the handler. We implements the handler
which skips the instruction caused the stall.

This patch depends on patch:
powerpc/85xx: Add platform_device declaration to fsl_pci.h

Signed-off-by: Zhao Chenhui &lt;b35336@freescale.com&gt;
Signed-off-by: Li Yang &lt;leoli@freescale.com&gt;
Signed-off-by: Liu Shuo &lt;soniccat.liu@gmail.com&gt;
Signed-off-by: Jia Hongtao &lt;hongtao.jia@freescale.com&gt;
Signed-off-by: Scott Wood &lt;scottwood@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/85xx: Add AltiVec support for e6500</title>
<updated>2013-03-12T20:59:26+00:00</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2012-09-07T20:57:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=cd66cc2ee52bca82f1b06e2fbc1ce63f33700190'/>
<id>cd66cc2ee52bca82f1b06e2fbc1ce63f33700190</id>
<content type='text'>
The e6500 core adds support for AltiVec on a Book-E class processor.
Connect up all the various exception handling code and build config
mechanisms to allow user spaces apps to utilize AltiVec.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The e6500 core adds support for AltiVec on a Book-E class processor.
Connect up all the various exception handling code and build config
mechanisms to allow user spaces apps to utilize AltiVec.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/booke: Add CPU_FTR_EMB_HV check for e5500.</title>
<updated>2012-09-12T19:57:09+00:00</updated>
<author>
<name>Varun Sethi</name>
<email>Varun.Sethi@freescale.com</email>
</author>
<published>2012-07-09T13:04:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=39be5b4a7f232870aad0b3c130791eacd0d34347'/>
<id>39be5b4a7f232870aad0b3c130791eacd0d34347</id>
<content type='text'>
Added CPU_FTR_EMB_HV feature check for e5500.

Signed-off-by: Varun Sethi &lt;Varun.Sethi@freescale.com&gt;
Signed-off-by: Mihai Caraman &lt;mihai.caraman@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Added CPU_FTR_EMB_HV feature check for e5500.

Signed-off-by: Varun Sethi &lt;Varun.Sethi@freescale.com&gt;
Signed-off-by: Mihai Caraman &lt;mihai.caraman@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/booke: Separate out restore_e5500/setup_e5500 routines.</title>
<updated>2012-09-12T19:57:09+00:00</updated>
<author>
<name>Varun Sethi</name>
<email>Varun.Sethi@freescale.com</email>
</author>
<published>2012-07-09T13:01:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=0778407f836d632cce90e5d9df490a7c5e6e398a'/>
<id>0778407f836d632cce90e5d9df490a7c5e6e398a</id>
<content type='text'>
For the 64 bit case separate out e5500 cpu_setup and cpu_restore functions.
The cpu_setup function (for the primary core) is passed the cpu_spec
pointer, which is not there in case of the cpu_restore function. Also, in
our case we will have to manipulate the CPU_FTR_EMB_HV flag on the primary
core.

Signed-off-by: Varun Sethi &lt;Varun.Sethi@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
For the 64 bit case separate out e5500 cpu_setup and cpu_restore functions.
The cpu_setup function (for the primary core) is passed the cpu_spec
pointer, which is not there in case of the cpu_restore function. Also, in
our case we will have to manipulate the CPU_FTR_EMB_HV flag on the primary
core.

Signed-off-by: Varun Sethi &lt;Varun.Sethi@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/booke: Merge the 32 bit e5500/e500mc cpu setup code.</title>
<updated>2012-09-12T19:57:09+00:00</updated>
<author>
<name>Varun Sethi</name>
<email>Varun.Sethi@freescale.com</email>
</author>
<published>2012-07-09T12:58:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=2c71b0cc4a626d8bd02b88b3b92ce18be4d54c6d'/>
<id>2c71b0cc4a626d8bd02b88b3b92ce18be4d54c6d</id>
<content type='text'>
Merge the 32 bit cpu setup code for e500mc/e5500 and define the
"cpu_restore" routine (for e5500/e6500) only for the 64 bit case. The
cpu_restore routine is used in the 64 bit case for setting up the secondary
cores.

Signed-off-by: Varun Sethi &lt;Varun.Sethi@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Merge the 32 bit cpu setup code for e500mc/e5500 and define the
"cpu_restore" routine (for e5500/e6500) only for the 64 bit case. The
cpu_restore routine is used in the 64 bit case for setting up the secondary
cores.

Signed-off-by: Varun Sethi &lt;Varun.Sethi@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
