linux-toradex.git/arch/powerpc/kernel/head_32.S, branch v2.6.36

KVM: PPC: Add KVM intercept handlers

2010-05-17T09:18:52+00:00

When an interrupt occurs we don't know yet if we're in guest context or
in host context. When in guest context, KVM needs to handle it.

So let's pull the same trick we did on Book3S_64: Just add a macro to
determine if we're in guest context or not and if so jump on to KVM code.

CC: Benjamin Herrenschmidt 
Signed-off-by: Alexander Graf 
Acked-by: Benjamin Herrenschmidt 
Signed-off-by: Avi Kivity

powerpc: gamecube/wii: early debugging using usbgecko

2009-12-13T05:24:31+00:00

Add support for using the USB Gecko adapter as an early debugging
console on the Nintendo GameCube and Wii video game consoles.
The USB Gecko is a 3rd party memory card interface adapter that provides
a EXI (External Interface) to USB serial converter.

Signed-off-by: Albert Herranz 
Acked-by: Benjamin Herrenschmidt 
Signed-off-by: Grant Likely

powerpc: Use names rather than numbers for SPRGs (v2)

2009-08-20T00:12:27+00:00

The kernel uses SPRG registers for various purposes, typically in
low level assembly code as scratch registers or to hold per-cpu
global infos such as the PACA or the current thread_info pointer.

We want to be able to easily shuffle the usage of those registers
as some implementations have specific constraints realted to some
of them, for example, some have userspace readable aliases, etc..
and the current choice isn't always the best.

This patch should not change any code generation, and replaces the
usage of SPRN_SPRGn everywhere in the kernel with a named replacement
and adds documentation next to the definition of the names as to
what those are used for on each processor family.

The only parts that still use the original numbers are bits of KVM
or suspend/resume code that just blindly needs to save/restore all
the SPRGs.

Signed-off-by: Benjamin Herrenschmidt

powerpc: Map more memory early on 601 processors

2009-06-26T04:37:25+00:00

The 32-bit kernel relies on some memory being mapped covering
the kernel text,data and bss at least, early during boot before
the full MMU setup is done. On 32-bit "classic" processors, this
is done using BAT registers.

On 601, the size of BATs is limited to 8M and we use 2 of them
for that initial mapping. This can become quite tight when enabling
features like lockdep, so let's use a 3rd one to bump that mapping
from 16M to 24M. We keep the 4th BAT free as it can be useful for
debugging early boot code to map things like serial ports.

Signed-off-by: Benjamin Herrenschmidt

powerpc: Fix bug in move of altivec code to vector.S

2009-06-12T06:51:41+00:00

The patch that moved to vector.S and made common between 32 and 64-bit the
altivec code had a nasty bug on 32-bit (did I really test that ?) which
causes the kernel to blr back into userspace ... oops :-)

Signed-off-by: Benjamin Herrenschmidt

powerpc: Move VMX and VSX asm code to vector.S

2009-06-09T06:46:25+00:00

Currently, load_up_altivec and give_up_altivec are duplicated
in 32-bit and 64-bit. This creates a common implementation that
is moved away from head_32.S, head_64.S and misc_64.S and into
vector.S, using the same macros we already use for our common
implementation of load_up_fpu.

I also moved the VSX code over to vector.S though in that case
I didn't make it build on 32-bit (yet).

Signed-off-by: Benjamin Herrenschmidt

powerpc: convert to use __HEAD and HEAD_TEXT macros.

2009-04-26T16:20:38+00:00

This has the consequence of changing the section name use for head
code from ".text.head" to ".head.text".  Since this commit changes all
users in the architecture, this change should be harmless.

Signed-off-by: Tim Abbott 
Cc: Benjamin Herrenschmidt 
Acked-by: Sam Ravnborg 
Signed-off-by: Linus Torvalds

powerpc/mm: e300c2/c3/c4 TLB errata workaround

2009-03-24T02:47:32+00:00

Complete workaround for DTLB errata in e300c2/c3/c4 processors.

Due to the bug, the hardware-implemented LRU algorythm always goes to way
1 of the TLB. This fix implements the proposed software workaround in
form of a LRW table for chosing the TLB-way.

Based on patch from David Jander 

Signed-off-by: Kumar Gala 
Signed-off-by: Benjamin Herrenschmidt

powerpc/mm: Used free register to save a few cycles in SW TLB miss handling

2009-03-24T02:47:31+00:00

Now that r0 is free we can keep the value of I/DMISS in r3 and not reload
it before doing the tlbli/d.  This saves us a few cycles in the fast path
case.

Signed-off-by: Kumar Gala 
Signed-off-by: Benjamin Herrenschmidt

powerpc/mm: Remove unused register usage in SW TLB miss handling

2009-03-24T02:47:31+00:00

Long ago we had some code that actually used the CTR in the SW TLB
miss handlers (603/e300).  Since we don't use it no reason to waste
cycles saving it off and restoring it (we actually didn't restore it
in the fast path case).

Signed-off-by: Kumar Gala 
Signed-off-by: Benjamin Herrenschmidt