linux-toradex.git/arch/powerpc/kernel/head_8xx.S, branch v4.4.10

powerpc/8xx: Implementation of PAGE_EXEC

2015-06-03T02:37:28+00:00

This patch implements PAGE_EXEC capability on the 8xx.

All pages PP exec bits are set to 000, which means Execute for
Supervisor and no Execute for User.
Then we use the APG to say whether accesses are according to Page
rules, "all Supervisor" rules (Exec for all) and
"all User" rules (Exec for noone)

Therefore, we define 4 APG groups. msb is _PAGE_EXEC,
lsb is _PAGE_USER. MI_AP is initialised as follows:
GP0 (00) => Not User, no exec => 11 (all accesses performed as user)
GP1 (01) => User but no exec => 11 (all accesses performed as user)
GP2 (10) => Not User, exec => 01 (rights according to page definition)
GP3 (11) => User, exec => 00 (all accesses performed as supervisor)

Signed-off-by: Christophe Leroy 
[scottwood: comments: s/exec/data/ on data side, and s/pages/pages'/]
Signed-off-by: Scott Wood

powerpc/8xx: Handle PAGE_USER via APG bits

2015-06-03T02:37:27+00:00

Use of APG for handling PAGE_USER.

All pages PP exec bits are set to either 000 or 011, which means
respectively RW for Supervisor and no access for User, or RO for
Supervisor and no access for user.

Then we use the APG to say whether accesses are according to
Page rules or "all Supervisor" rules (Access to all)

Therefore, we define 2 APG groups corresponding to _PAGE_USER.
Mx_AP are initialised as follows:
GP0 => No user => 01 (all accesses performed according
				to page definition)
GP1 => User => 00 (all accesses performed as supervisor
                                according to page definition)

This removes the special 8xx handling in pte_update()

Signed-off-by: Christophe Leroy 
Signed-off-by: Scott Wood

powerpc/8xx: Add support for TASK_SIZE greater than 0x80000000

2015-06-03T02:37:26+00:00

By default, TASK_SIZE is set to 0x80000000 for PPC_8xx, which is most
likely sufficient for most cases. However, kernel configuration allows
to set TASK_SIZE to another value, so the 8xx shall handle it.

This patch also takes into account the case of PAGE_OFFSET lower than
0x80000000, allthought most of the time it is equal to 0xC0000000

Signed-off-by: Christophe Leroy 
Signed-off-by: Scott Wood

powerpc/8xx: Use SPRG2 instead of DAR for saving r3

2015-06-03T02:37:26+00:00

We now have SPRG2 available as in it not used anymore for saving CR, so we don't
need to crash DAR anymore for saving r3 for CPU6 ERRATA handling.

Signed-off-by: Christophe Leroy 
Signed-off-by: Scott Wood

powerpc/8xx: dont save CR in SCRATCH registers

2015-06-03T02:37:26+00:00

CR only needs to be preserved when checking if we are handling a kernel address.
So we can preserve CR in a register:
- In ITLBMiss, check is done only when CONFIG_MODULES is defined. Otherwise we
don't need to do anything at all with CR.
- We use r10, then we reload SRR0/MD_EPN into r10 when CR is restored

Signed-off-by: Christophe Leroy 
Signed-off-by: Scott Wood

powerpc/8xx: Handle CR out of exception PROLOG/EPILOG

2015-06-03T02:37:25+00:00

In order to be able to reduce scope during which CR is saved, we take
CR saving/restoring out of exception PROLOG and EPILOG

Signed-off-by: Christophe Leroy 
Signed-off-by: Scott Wood

powerpc/8xx: macro for handling CPU15 errata

2015-06-03T02:37:25+00:00

Having a macro will help keep clear code.

Signed-off-by: Christophe Leroy 
Signed-off-by: Scott Wood

powerpc/8xx: Remove duplicated code in set_context()

2015-01-30T03:59:02+00:00

Signed-off-by: Christophe Leroy 
Signed-off-by: Scott Wood

powerpc/8xx: Optimise access to swapper_pg_dir

2015-01-30T03:59:02+00:00

All accessed to PGD entries are done via 0(r11).
By using lower part of swapper_pg_dir as load index to r11, we can remove the
ori instruction.

Signed-off-by: Christophe Leroy 
Signed-off-by: Scott Wood

powerpc/8xx: Take benefit of aligned PGDIR

2015-01-30T03:59:02+00:00

L1 base address is now aligned so we can insert L1 index into r11 directly and
then preserve r10

Signed-off-by: Christophe Leroy 
Signed-off-by: Scott Wood