linux-toradex.git/arch/powerpc/kernel/kvm_emul.S, branch v3.4.2

KVM: PPC: Avoid patching paravirt template code

2012-03-05T12:52:34+00:00

Currently we patch the whole code include paravirt template code.
This isn't safe for scratch area and has impact to performance.

Signed-off-by: Liu Yu 
Signed-off-by: Alexander Graf 
Signed-off-by: Avi Kivity

KVM: PPC: booke: Paravirtualize wrtee

2012-03-05T12:52:26+00:00

Also fix wrteei 1 paravirt to check for a pending interrupt.

Signed-off-by: Scott Wood 
Signed-off-by: Alexander Graf 
Signed-off-by: Avi Kivity

PPC: Fix race in mtmsr paravirt implementation

2012-03-05T12:52:24+00:00

The current implementation of mtmsr and mtmsrd are racy in that it does:

  * check (int_pending == 0)
  ---> host sets int_pending = 1 <---
  * write shared page
  * done

while instead we should check for int_pending after the shared page is written.

Signed-off-by: Bharat Bhushan 
Signed-off-by: Alexander Graf 
Signed-off-by: Avi Kivity

KVM: PPC: Make PV mtmsrd L=1 work with r30 and r31

2010-10-24T08:52:14+00:00

We had an arbitrary limitation in mtmsrd L=1 that kept us from using r30 and
r31 as input registers. Let's get rid of that and get more potential speedups!

Signed-off-by: Alexander Graf

KVM: PPC: Make PV mtmsr work with r30 and r31

2010-10-24T08:52:13+00:00

So far we've been restricting ourselves to r0-r29 as registers an mtmsr
instruction could use. This was bad, as there are some code paths in
Linux actually using r30.

So let's instead handle all registers gracefully and get rid of that
stupid limitation

Signed-off-by: Alexander Graf

KVM: PPC: Add mtsrin PV code

2010-10-24T08:52:12+00:00

This is the guest side of the mtsr acceleration. Using this a guest can now
call mtsrin with almost no overhead as long as it ensures that it only uses
it with (MSR_IR|MSR_DR) == 0. Linux does that, so we're good.

Signed-off-by: Alexander Graf

KVM: PPC: PV wrteei

2010-10-24T08:50:57+00:00

On BookE the preferred way to write the EE bit is the wrteei instruction. It
already encodes the EE bit in the instruction.

So in order to get BookE some speedups as well, let's also PV'nize thati
instruction.

Signed-off-by: Alexander Graf 
Signed-off-by: Avi Kivity

KVM: PPC: PV mtmsrd L=0 and mtmsr

2010-10-24T08:50:56+00:00

There is also a form of mtmsr where all bits need to be addressed. While the
PPC64 Linux kernel behaves resonably well here, on PPC32 we do not have an
L=1 form. It does mtmsr even for simple things like only changing EE.

So we need to hook into that one as well and check for a mask of bits that we
deem safe to change from within guest context.

Signed-off-by: Alexander Graf 
Signed-off-by: Avi Kivity

KVM: PPC: PV mtmsrd L=1

2010-10-24T08:50:56+00:00

The PowerPC ISA has a special instruction for mtmsr that only changes the EE
and RI bits, namely the L=1 form.

Since that one is reasonably often occuring and simple to implement, let's
go with this first. Writing EE=0 is always just a store. Doing EE=1 also
requires us to check for pending interrupts and if necessary exit back to the
hypervisor.

Signed-off-by: Alexander Graf 
Signed-off-by: Avi Kivity

KVM: PPC: PV assembler helpers

2010-10-24T08:50:55+00:00

When we hook an instruction we need to make sure we don't clobber any of
the registers at that point. So we write them out to scratch space in the
magic page. To make sure we don't fall into a race with another piece of
hooked code, we need to disable interrupts.

To make the later patches and code in general easier readable, let's introduce
a set of defines that save and restore r30, r31 and cr. Let's also define some
helpers to read the lower 32 bits of a 64 bit field on 32 bit systems.

Signed-off-by: Alexander Graf 
Signed-off-by: Avi Kivity