<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-toradex.git/arch/powerpc/kernel/misc_32.S, branch v3.6.10</title>
<subtitle>Linux kernel for Apalis and Colibri modules</subtitle>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/'/>
<entry>
<title>powerpc: Use CURRENT_THREAD_INFO instead of open coded assembly</title>
<updated>2012-07-11T04:18:22+00:00</updated>
<author>
<name>Stuart Yoder</name>
<email>stuart.yoder@freescale.com</email>
</author>
<published>2012-07-05T04:41:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=9778b696a0188ad3b3524b383953ee73b31b7b68'/>
<id>9778b696a0188ad3b3524b383953ee73b31b7b68</id>
<content type='text'>
Signed-off-by: Stuart Yoder &lt;stuart.yoder@freescale.com&gt;
Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Signed-off-by: Stuart Yoder &lt;stuart.yoder@freescale.com&gt;
Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/47x: Kernel support for KEXEC</title>
<updated>2012-05-03T12:40:23+00:00</updated>
<author>
<name>Suzuki Poulose</name>
<email>suzuki@in.ibm.com</email>
</author>
<published>2012-04-15T22:27:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=68343020031585f861d93e2f25589598feadaff3'/>
<id>68343020031585f861d93e2f25589598feadaff3</id>
<content type='text'>
This patch adds support for creating 1:1 mapping for the PPC_47x during
a KEXEC. The implementation is similar to that of the PPC440x which is
described here :

	http://patchwork.ozlabs.org/patch/104323/

PPC_47x MMU :

The 47x uses Unified TLB 1024 entries, with 4-way associative mapping
(4 x 256 entries). The index to be used is calculated by the MMU by
hashing the PID, EPN and TS. The software can choose to specify the way
by setting bit 0(enable way select) and the way in bits 1-2 in the TLB
Word 0.

Implementation:

The patch erases all the UTLB entries which includes the tlb covering
the mapping for our code. The shadow TLB caches the mapping for the
running code which helps us to continue the execution until we do
isync/rfi. We then create a tmp mapping for the current code in the
other address space (TS) and switch to it.

Then we create a 1:1 mapping(EPN=RPN) for 0-2GiB in the original
address space and switch to the new mapping.

TODO: Add SMP support.

Signed-off-by: Suzuki K. Poulose &lt;suzuki@in.ibm.com&gt;
Signed-off-by: Josh Boyer &lt;jwboyer@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch adds support for creating 1:1 mapping for the PPC_47x during
a KEXEC. The implementation is similar to that of the PPC440x which is
described here :

	http://patchwork.ozlabs.org/patch/104323/

PPC_47x MMU :

The 47x uses Unified TLB 1024 entries, with 4-way associative mapping
(4 x 256 entries). The index to be used is calculated by the MMU by
hashing the PID, EPN and TS. The software can choose to specify the way
by setting bit 0(enable way select) and the way in bits 1-2 in the TLB
Word 0.

Implementation:

The patch erases all the UTLB entries which includes the tlb covering
the mapping for our code. The shadow TLB caches the mapping for the
running code which helps us to continue the execution until we do
isync/rfi. We then create a tmp mapping for the current code in the
other address space (TS) and switch to it.

Then we create a 1:1 mapping(EPN=RPN) for 0-2GiB in the original
address space and switch to the new mapping.

TODO: Add SMP support.

Signed-off-by: Suzuki K. Poulose &lt;suzuki@in.ibm.com&gt;
Signed-off-by: Josh Boyer &lt;jwboyer@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/44x: Fix/Initialize PID to kernel PID before the TLB search</title>
<updated>2012-05-03T12:37:36+00:00</updated>
<author>
<name>Suzuki Poulose</name>
<email>suzuki@in.ibm.com</email>
</author>
<published>2012-04-15T21:48:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=f13bfcc6961a5c9f511c401292db522edcd0b061'/>
<id>f13bfcc6961a5c9f511c401292db522edcd0b061</id>
<content type='text'>
Initialize the PID register with kernel pid (0) before we start
setting the TLB mapping for KEXEC. Also set the MMUCR[TID] to kernel
PID.

This was spotted while testing the kexec on ISS for 47x. ISS  doesn't
return a successful tlbsx for a kernel address with PID set to a user PID.
Though the hardware/qemu/simics work fine.

This patch is harmless and initializes the PID to 0 (kernel PID) which
is usually the case during a normal kernel boot. This would fix the kexec
on ISS for 440. I have tested this patch on sequoia board.

Signed-off-by: Suzuki K Poulose &lt;suzuki@in.ibm.com&gt;
Cc: Josh Boyer &lt;jwboyer@gmail.com&gt;
Signed-off-by: Josh Boyer &lt;jwboyer@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Initialize the PID register with kernel pid (0) before we start
setting the TLB mapping for KEXEC. Also set the MMUCR[TID] to kernel
PID.

This was spotted while testing the kexec on ISS for 47x. ISS  doesn't
return a successful tlbsx for a kernel address with PID set to a user PID.
Though the hardware/qemu/simics work fine.

This patch is harmless and initializes the PID to 0 (kernel PID) which
is usually the case during a normal kernel boot. This would fix the kexec
on ISS for 440. I have tested this patch on sequoia board.

Signed-off-by: Suzuki K Poulose &lt;suzuki@in.ibm.com&gt;
Cc: Josh Boyer &lt;jwboyer@gmail.com&gt;
Signed-off-by: Josh Boyer &lt;jwboyer@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/4xx: Fix typos in kexec config dependencies</title>
<updated>2011-11-16T03:47:54+00:00</updated>
<author>
<name>Suzuki Poulose</name>
<email>suzuki@in.ibm.com</email>
</author>
<published>2011-11-14T16:43:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=bbc24a25e29136a56cf5015ef23eb2c2e8828023'/>
<id>bbc24a25e29136a56cf5015ef23eb2c2e8828023</id>
<content type='text'>
Kexec is not supported on 47x. 47x is a variant of 44x with slightly
different MMU and SMP support. There was a typo in the config dependency
for kexec. This patch fixes the same.

Signed-off-by: Suzuki K. Poulose &lt;suzuki@in.ibm.com&gt;
Signed-off-by: Paul Bolle &lt;pebolle@tiscali.nl&gt;
Cc:	Kumar Gala &lt;galak@kernel.crashing.org&gt;
Cc:	Josh Boyer &lt;jwboyer@gmail.com&gt;
Cc:	linux ppc dev &lt;linuxppc-dev@lists.ozlabs.org&gt;
Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Kexec is not supported on 47x. 47x is a variant of 44x with slightly
different MMU and SMP support. There was a typo in the config dependency
for kexec. This patch fixes the same.

Signed-off-by: Suzuki K. Poulose &lt;suzuki@in.ibm.com&gt;
Signed-off-by: Paul Bolle &lt;pebolle@tiscali.nl&gt;
Cc:	Kumar Gala &lt;galak@kernel.crashing.org&gt;
Cc:	Josh Boyer &lt;jwboyer@gmail.com&gt;
Cc:	linux ppc dev &lt;linuxppc-dev@lists.ozlabs.org&gt;
Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/44x: Kexec support for PPC440X chipsets</title>
<updated>2011-08-11T17:50:37+00:00</updated>
<author>
<name>Suzuki Poulose</name>
<email>suzuki@in.ibm.com</email>
</author>
<published>2011-07-18T03:29:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=674bfa485554156aa90ce17288712fcb568a42c3'/>
<id>674bfa485554156aa90ce17288712fcb568a42c3</id>
<content type='text'>
This patch adds kexec support for PPC440 based chipsets.  This work is based
on the KEXEC patches for FSL BookE.

The FSL BookE patch and the code flow could be found at the link below:

	http://patchwork.ozlabs.org/patch/49359/

Steps:

1) Invalidate all the TLB entries except the one this code is run from
2) Create a tmp mapping for our code in the other address space and jump to it
3) Invalidate the entry we used
4) Create a 1:1 mapping for 0-2GiB in blocks of 256M
5) Jump to the new 1:1 mapping and invalidate the tmp mapping

I have tested this patches on Ebony, Sequoia boards and Virtex on QEMU.

You need kexec-tools commit e8b7939b1e or newer for ppc440x support, 
available at:

 git://git.kernel.org/pub/scm/utils/kernel/kexec/kexec-tools.git

Signed-off-by: 	Suzuki Poulose &lt;suzuki@in.ibm.com&gt;
Cc:	Sebastian Andrzej Siewior &lt;bigeasy@linutronix.de&gt;
Signed-off-by: Josh Boyer &lt;jwboyer@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch adds kexec support for PPC440 based chipsets.  This work is based
on the KEXEC patches for FSL BookE.

The FSL BookE patch and the code flow could be found at the link below:

	http://patchwork.ozlabs.org/patch/49359/

Steps:

1) Invalidate all the TLB entries except the one this code is run from
2) Create a tmp mapping for our code in the other address space and jump to it
3) Invalidate the entry we used
4) Create a 1:1 mapping for 0-2GiB in blocks of 256M
5) Jump to the new 1:1 mapping and invalidate the tmp mapping

I have tested this patches on Ebony, Sequoia boards and Virtex on QEMU.

You need kexec-tools commit e8b7939b1e or newer for ppc440x support, 
available at:

 git://git.kernel.org/pub/scm/utils/kernel/kexec/kexec-tools.git

Signed-off-by: 	Suzuki Poulose &lt;suzuki@in.ibm.com&gt;
Cc:	Sebastian Andrzej Siewior &lt;bigeasy@linutronix.de&gt;
Signed-off-by: Josh Boyer &lt;jwboyer@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc: Fix 32-bit SMP build</title>
<updated>2011-05-20T23:23:19+00:00</updated>
<author>
<name>Josh Boyer</name>
<email>jwboyer@linux.vnet.ibm.com</email>
</author>
<published>2011-05-20T20:22:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=6de06f313a65d0ecabf055e708d082002b568866'/>
<id>6de06f313a65d0ecabf055e708d082002b568866</id>
<content type='text'>
Commit 69e3cea8d5fd526 ("powerpc/smp: Make start_secondary_resume
available to all CPU variants") introduced start_secondary_resume to
misc_32.S, however it uses a 64-bit instruction which is not valid on
32-bit platforms.  Use 'stw' instead.

Reported-by: Richard Cochran &lt;richardcochran@gmail.com&gt;
Tested-by: Richard Cochran &lt;richardcochran@gmail.com&gt;
Signed-off-by: Josh Boyer &lt;jwboyer@linux.vnet.ibm.com&gt;
Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
Signed-off-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Commit 69e3cea8d5fd526 ("powerpc/smp: Make start_secondary_resume
available to all CPU variants") introduced start_secondary_resume to
misc_32.S, however it uses a 64-bit instruction which is not valid on
32-bit platforms.  Use 'stw' instead.

Reported-by: Richard Cochran &lt;richardcochran@gmail.com&gt;
Tested-by: Richard Cochran &lt;richardcochran@gmail.com&gt;
Signed-off-by: Josh Boyer &lt;jwboyer@linux.vnet.ibm.com&gt;
Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
Signed-off-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/smp: Make start_secondary_resume available to all CPU variants</title>
<updated>2011-05-19T03:07:12+00:00</updated>
<author>
<name>Benjamin Herrenschmidt</name>
<email>benh@kernel.crashing.org</email>
</author>
<published>2011-05-19T03:07:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=69e3cea8d5fd52677f2b6219542d0f8b53fe4c80'/>
<id>69e3cea8d5fd52677f2b6219542d0f8b53fe4c80</id>
<content type='text'>
This should fix SMP &amp; Hotplug builds on FSL BookE and 476

Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This should fix SMP &amp; Hotplug builds on FSL BookE and 476

Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc: Remove second definition of STACK_FRAME_OVERHEAD</title>
<updated>2010-11-29T04:48:23+00:00</updated>
<author>
<name>Stephen Rothwell</name>
<email>sfr@canb.auug.org.au</email>
</author>
<published>2010-11-18T15:06:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=46f5221049bb46b0188aad6b6dfab5dbc778be22'/>
<id>46f5221049bb46b0188aad6b6dfab5dbc778be22</id>
<content type='text'>
Since STACK_FRAME_OVERHEAD is defined in asm/ptrace.h and that
is ASSEMBER safe, we can just include that instead of going via
asm-offsets.h.

Signed-off-by: Stephen Rothwell &lt;sfr@canb.auug.org.au&gt;
Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Since STACK_FRAME_OVERHEAD is defined in asm/ptrace.h and that
is ASSEMBER safe, we can just include that instead of going via
asm-offsets.h.

Signed-off-by: Stephen Rothwell &lt;sfr@canb.auug.org.au&gt;
Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/kexec: Adds correct calling convention for kexec purgatory</title>
<updated>2010-08-31T01:35:12+00:00</updated>
<author>
<name>Matthew McClintock</name>
<email>msm@freescale.com</email>
</author>
<published>2010-08-27T11:58:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=4562c986f0d694124de20815adf7e1aad8a94668'/>
<id>4562c986f0d694124de20815adf7e1aad8a94668</id>
<content type='text'>
Call kexec purgatory code correctly. We were getting lucky before.
If you examine the powerpc 32bit kexec "purgatory" code you will
see it expects the following:

&gt;From kexec-tools: purgatory/arch/ppc/v2wrap_32.S
-&gt; calling convention:
-&gt;   r3 = physical number of this cpu (all cpus)
-&gt;   r4 = address of this chunk (master only)

As such, we need to set r3 to the current core, r4 happens to be
unused by purgatory at the moment but we go ahead and set it
here as well

Signed-off-by: Matthew McClintock &lt;msm@freescale.com&gt;
Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Call kexec purgatory code correctly. We were getting lucky before.
If you examine the powerpc 32bit kexec "purgatory" code you will
see it expects the following:

&gt;From kexec-tools: purgatory/arch/ppc/v2wrap_32.S
-&gt; calling convention:
-&gt;   r3 = physical number of this cpu (all cpus)
-&gt;   r4 = address of this chunk (master only)

As such, we need to set r3 to the current core, r4 happens to be
unused by purgatory at the moment but we go ahead and set it
here as well

Signed-off-by: Matthew McClintock &lt;msm@freescale.com&gt;
Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc: Unconditionally enabled irq stacks</title>
<updated>2010-06-15T05:02:37+00:00</updated>
<author>
<name>Christoph Hellwig</name>
<email>hch@lst.de</email>
</author>
<published>2010-06-02T22:24:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=f1ba9a5b2ab7d3f5a910d93371c4f22b636b7683'/>
<id>f1ba9a5b2ab7d3f5a910d93371c4f22b636b7683</id>
<content type='text'>
Irq stacks provide an essential protection from stack overflows through
external interrupts, at the cost of two additionals stacks per CPU.

Enable them unconditionally to simplify the kernel build and prevent
people from accidentally disabling them.

Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Irq stacks provide an essential protection from stack overflows through
external interrupts, at the cost of two additionals stacks per CPU.

Enable them unconditionally to simplify the kernel build and prevent
people from accidentally disabling them.

Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
