linux-toradex.git/arch/powerpc/sysdev/Makefile, branch v2.6.27.12

powerpc: Remove use of CONFIG_PPC_MERGE

2008-08-04T03:18:17+00:00

Now that arch/ppc is gone and CONFIG_PPC_MERGE is always set, remove
the dead code associated with !CONFIG_PPC_MERGE from arch/powerpc
and include/asm-powerpc.

Signed-off-by: Kumar Gala 
Signed-off-by: Paul Mackerras

powerpc/QE: switch to the cpm_muram implementation

2008-06-10T16:11:21+00:00

This is very trivial patch. We're transitioning to the cpm_muram_*
calls. That's it.

Less trivial changes:
- BD_SC_* defines were defined in the cpm.h and qe.h, so to avoid redefines
  we remove BD_SC from the qe.h and use cpm.h along with cpm_muram_*
  prototypes;
- qe_muram_dump was unused and thus removed;
- added some code to the cpm_common.c to support legacy QE bindings
  (data-only node name).
- For convenience, define qe_* calls to cpm_*. So drivers need not to be
  changed.

Signed-off-by: Anton Vorontsov 
Signed-off-by: Kumar Gala

powerpc/sysdev: implement FSL GTM support

2008-06-10T15:38:50+00:00

GTM stands for General-purpose Timers Module and able to generate
timer{1,2,3,4} interrupts. These timers are used by the drivers that
need time precise interrupts (like for USB transactions scheduling for
the Freescale USB Host controller as found in some QE and CPM chips),
or these timers could be used as wakeup events from the CPU deep-sleep
mode.

Things unimplemented:
1. Cascaded (32 bit) timers (1-2, 3-4).
   This is straightforward to implement when needed, two timers should
   be marked as "requested" and configured as appropriate.
2. Super-cascaded (64 bit) timers (1-2-3-4).
   This is also straightforward to implement when needed, all timers
   should be marked as "requested" and configured as appropriate.

Signed-off-by: Anton Vorontsov 
Signed-off-by: Kumar Gala

[POWERPC] fsl: PCIe MSI support for 83xx/85xx/86xx processors.

2008-06-02T19:44:24+00:00

This MSI driver can be used on 83xx/85xx/86xx board.
In this driver, virtual interrupt host and chip were
setup. There are 256 MSI interrupts in this host, Every 32
MSI interrupts cascaded to one IPIC/MPIC interrupt.
The chip was treated as edge sensitive and some necessary
functions were setup for this chip.

Before using the MSI interrupt, PCI/PCIE device need to
ask for a MSI interrupt in the 256 MSI interrupts. A 256bit
bitmap show which MSI interrupt was used, reserve bit in
the bitmap can be used to force the device use some designate
MSI interrupt in the 256 MSI interrupts. Sometimes this is useful
for testing the all the MSI interrupts. The msi-available-ranges
property in the dts file was used for this purpose.

Signed-off-by: Jason Jin 
Signed-off-by: Kumar Gala

[POWERPC] Add 6xx-style HID0_SLEEP support.

2008-05-16T13:22:28+00:00

This adds a function to put a 6xx/7xx/7xxx/83xx family CPU into sleep
mode, and return after an interrupt has occurred.  It expects to be
called with interrupts disabled, and returns with interrupts disabled.
Interrupts are enabled while the processor is asleep, but the interrupt
that wakes the processor is not handled; it is still pending when this
function returns.

Signed-off-by: Scott Wood 
Signed-off-by: Guennadi Liakhovetski 
Signed-off-by: Paul Mackerras

[POWERPC] fsl_lbc: implement few UPM routines

2008-04-17T06:01:38+00:00

Freescale UPM can be used to adjust localbus timings or to generate
orbitrary, pre-programmed "patterns" on the external Localbus signals.
This patch implements few routines so drivers could work with UPMs in
safe and generic manner.

So far there is just one user of these routines: Freescale UPM NAND
driver.

Signed-off-by: Anton Vorontsov 
Signed-off-by: Kumar Gala

[POWERPC] 4xx: Add PPC4xx L2-cache support (440GX)

2008-03-26T12:27:54+00:00

This patch adds support for the 256k L2 cache found on some IBM/AMCC
4xx PPC's. It introduces a common 4xx SoC file (sysdev/ppc4xx_soc.c)
which currently "only" adds the L2 cache init code. Other common 4xx
stuff can be added later here.

The L2 cache handling code is a copy of Eugene's code in arch/ppc
with small modifications.

Tested on AMCC Taishan 440GX.

Signed-off-by: Stefan Roese 
Signed-off-by: Josh Boyer

[POWERPC] CPM: Rename commproc to cpm1 and cpm2_common.c to cpm2.c

2008-01-28T14:31:05+00:00

Rename commproc.[ch] to cpm1.[ch] to be more consistent with cpm2. Also
rename cpm2_common.c to cpm2.c as suggested by Scott Wood. Adjust the
includes accordingly.

Signed-off-by: Jochen Friedrich 
Signed-off-by: Kumar Gala

[POWERPC] Enable RTC for Ebony and Walnut (v2)

2008-01-25T13:07:26+00:00

This patch extends the Ebony and Walnut platform code to instantiate
the existing ds1742 RTC class driver for the DS1743 RTC/NVRAM chip
found on both those boards.  The patch uses a helper function to scan
the device tree and instantiate the appropriate platform_device based
on it, so it should be easy to extend for other boards which have mmio
mapped RTC chips.

Along with this, the device tree binding for the ds1743 chips is
tweaked, based on the existing DS1385 OF binding found at:
	http://playground.sun.com/1275/proposals/Closed/Remanded/Accepted/346-it.txt
Although that document covers the NVRAM portion of the chip, whereas
here we're interested in the RTC portion, so it's not entirely clear
if that's a good model.

This implements only RTC class driver support - that is /dev/rtc0, not
/dev/rtc, and the low-level get/set time callbacks remain
unimplemented.  That means in order to get at the clock you will
either need a modified version of hwclock which will look at
/dev/rtc0, or you'll need to configure udev to symlink rtc0 to rtc.

Signed-off-by: David Gibson 
Signed-off-by: Josh Boyer

[POWERPC] Move RapidIO support code from arch/ppc

2008-01-24T01:35:15+00:00

Do just enough to move the RapidIO support code for 85xx over from arch/ppc
into arch/powerpc and make it still build.

Signed-off-by: Kumar Gala