linux-toradex.git/arch/powerpc/sysdev/fsl_msi.h, branch v6.7

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 441

2019-06-05T15:37:17+00:00

Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license as published by
  the free software foundation version 2 of the license

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 315 file(s).

Signed-off-by: Thomas Gleixner 
Reviewed-by: Allison Randal 
Reviewed-by: Armijn Hemel 
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190531190115.503150771@linutronix.de
Signed-off-by: Greg Kroah-Hartman

powerpc/85xx: workaround for chips with MSI hardware errata

2015-03-24T00:51:18+00:00

The MPIC version 2.0 has a MSI errata (errata PIC1 of mpc8544), It causes
that neither MSI nor MSI-X can work fine. This is a workaround to allow
MSI-X to function properly.

Signed-off-by: Liu Shuo 
Signed-off-by: Li Yang 
Signed-off-by: Jia Hongtao 
Signed-off-by: Scott Wood

Revert "powerpc/fsl_msi: spread msi ints across different MSIRs"

2014-09-19T20:20:42+00:00

This reverts commit c822e73731fce3b49a4887140878d084d8a44c08.

This commit conflicted with a bitmap allocator change that partially
accomplishes the same thing, but which does so more correctly.  Revert
this one until it can be respun on top of the correct change.

Signed-off-by: Scott Wood

powerpc/fsl_msi: spread msi ints across different MSIRs

2014-09-04T23:51:45+00:00

Allocate msis such that each time a new interrupt is requested,
the SRS (MSIR register select) to be used is allocated in a
round-robin fashion.
The end result is that the msi interrupts will be spread across
distinct MSIRs with the main benefit that now users can set
affinity to each msi int through the mpic irq backing up the
MSIR register.
This is achieved with the help of a newly introduced msi bitmap
api that allows specifying the starting point when searching
for a free msi interrupt.

Signed-off-by: Laurentiu Tudor 
Cc: Scott Wood 
Cc: Mihai Caraman 
Signed-off-by: Scott Wood

powerpc/fsl_msi: reorganize structs to improve clarity and flexibility

2014-09-04T23:41:29+00:00

Store cascade_data in an array inside the driver
data for later use.
Get rid of the msi_virq array since now we can
encapsulate the virqs in the cascade_data
directly and access them through the array
mentioned earlier.

Signed-off-by: Laurentiu Tudor 
Cc: Scott Wood 
Cc: Mihai Caraman 
Signed-off-by: Scott Wood

powerpc/fsl_msi: add MSIIR1 support for MPIC v4.3

2013-08-07T23:38:05+00:00

The original MPIC MSI bank contains 8 registers, MPIC v4.3 MSI bank
contains 16 registers, and this patch adds NR_MSI_REG_MAX and
NR_MSI_IRQS_MAX to describe the maximum capability of MSI bank.
MPIC v4.3 provides MSIIR1 to index these 16 MSI registers. MSIIR1
uses different bits definition than MSIIR. This patch adds
ibs_shift and srs_shift to indicate the bits definition of the
MSIIR and MSIIR1, so the same code can handle the MSIIR and MSIIR1
simultaneously.

Signed-off-by: Minghuan Lian 
[scottwood@freescale.com: reinstated static on all_avail]
Signed-off-by: Scott Wood

irq_domain/powerpc: Use common irq_domain structure instead of irq_host

2012-02-14T21:06:50+00:00

This patch drops the powerpc-specific irq_host structures and uses the common
irq_domain strucutres defined in linux/irqdomain.h.  It also fixes all
the users to use the new structure names.

Renaming irq_host to irq_domain has been discussed for a long time, and this
patch is a step in the process of generalizing the powerpc virq code to be
usable by all architecture.

An astute reader will notice that this patch actually removes the irq_host
structure instead of renaming it.  This is because the irq_domain structure
already exists in include/linux/irqdomain.h and has the needed data members.

Signed-off-by: Grant Likely 
Cc: Benjamin Herrenschmidt 
Cc: Thomas Gleixner 
Cc: Milton Miller 
Tested-by: Olof Johansson

powerpc/fsl: add MSI support for the Freescale hypervisor

2012-01-04T21:47:44+00:00

Add support for vmpic-msi nodes to the fsl_msi driver.  The MSI is
virtualized by the hypervisor, so the vmpic-msi does not contain a 'reg'
property.  Instead, the driver uses hcalls.

Add support for the "msi-address-64" property to the fsl_pci driver.
The Freescale hypervisor typically puts the virtualized MSIIR register
in the page after the end of DDR, so we extend the DDR ATMU to cover it.
Any other location for MSIIR is not supported, for now.

Signed-off-by: Timur Tabi 
Signed-off-by: Kumar Gala

powerpc/fsl_msi: add support for the fsl, msi property in PCI nodes

2011-11-24T08:01:41+00:00

On Freescale parts with multiple MSI controllers, the controllers are
combined into one "pool" of interrupts.  Whenever a device requests an MSI
interrupt, the next available interrupt from the pool is selected,
regardless of which MSI controller the interrupt is from.  This works
because each PCI bus has an ATMU to all of CCSR, so any PCI device can
access any MSI interrupt register.

The fsl,msi property is used to specify that a given PCI bus should only
use a specific MSI device.  This is necessary, for example, with the
Freescale hypervisor, because the MSI devices are assigned to specific
partitions.

Ideally, we'd like to be able to assign MSI devices to PCI busses within
the MSI or PCI layers.  However, there does not appear to be a mechanism
to do that.  Whenever the MSI layer wants to allocate an MSI interrupt to
a PCI device, it just calls arch_setup_msi_irqs().  It would be nice if we
could register an MSI device with a specific PCI bus.

So instead we remember the phandles of each MSI device, and we use that to
limit our search for an available interrupt.  Whenever we are asked to
allocate a new interrupt for a PCI device, we check the fsl,msi property
of the PCI bus for that device.  If it exists, then as we are looping over
all MSI devices, we skip the ones that don't have a matching phandle.

Signed-off-by: Timur Tabi 
Signed-off-by: Kumar Gala

powerpc/fsl_msi: add support for "msi-address-64" property

2011-10-14T07:54:29+00:00

Add support for the msi-address-64 property of a PCI node.  This property
specifies the PCI address of MSIIR (message signaled interrupt index
register).

In commit 3da34aae ("powerpc/fsl: Support unique MSI addresses per PCIe Root
Complex"), the msi_addr_hi/msi_addr_lo fields of struct fsl_msi were redefined
from an actual address to just an offset, but the fields were not renamed
accordingly.  These fields are replace with a single field, msiir_offset,
to reflect the new meaning.

Signed-off-by: Timur Tabi 
Signed-off-by: Kumar Gala