<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-toradex.git/arch/powerpc/sysdev/indirect_pci.c, branch v3.4.2</title>
<subtitle>Linux kernel for Apalis and Colibri modules</subtitle>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/'/>
<entry>
<title>Fix common misspellings</title>
<updated>2011-03-31T14:26:23+00:00</updated>
<author>
<name>Lucas De Marchi</name>
<email>lucas.demarchi@profusion.mobi</email>
</author>
<published>2011-03-31T01:57:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=25985edcedea6396277003854657b5f3cb31a628'/>
<id>25985edcedea6396277003854657b5f3cb31a628</id>
<content type='text'>
Fixes generated by 'codespell' and manually reviewed.

Signed-off-by: Lucas De Marchi &lt;lucas.demarchi@profusion.mobi&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Fixes generated by 'codespell' and manually reviewed.

Signed-off-by: Lucas De Marchi &lt;lucas.demarchi@profusion.mobi&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/pci: Clean up direct access to sysdata by indirect ops</title>
<updated>2009-05-21T05:44:22+00:00</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2009-04-30T03:10:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=19afa40797a3b392b64bf0b30b46e62001eeb66f'/>
<id>19afa40797a3b392b64bf0b30b46e62001eeb66f</id>
<content type='text'>
We shouldn't directly access sysdata to get the pci_controller.  Instead
use pci_bus_to_host() for this purpose.  In the future we might have
sysdata be a device_node to match ppc64 and unify the code between ppc32
&amp; ppc64.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
We shouldn't directly access sysdata to get the pci_controller.  Instead
use pci_bus_to_host() for this purpose.  In the future we might have
sysdata be a device_node to match ppc64 and unify the code between ppc32
&amp; ppc64.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/4xx: Workaround for PPC440EPx/GRx PCI_28 Errata</title>
<updated>2008-06-17T23:01:38+00:00</updated>
<author>
<name>Josh Boyer</name>
<email>jwboyer@linux.vnet.ibm.com</email>
</author>
<published>2008-06-17T23:01:38+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=5ce4b59653b2c2053cd9a011918ac1e4747f24cc'/>
<id>5ce4b59653b2c2053cd9a011918ac1e4747f24cc</id>
<content type='text'>
The 440EPx/GRx chips don't support PCI MRM commands.  Drivers determine this
by looking for a zero value in the PCI cache line size register.  However,
some drivers write to this register upon initialization.  This can cause
MRMs to be used on these chips, which may cause deadlocks on PLB4.

The workaround implemented here introduces a new indirect_type flag, called
PPC_INDIRECT_TYPE_BROKEN_MRM.  This is set in the pci_controller structure in
the pci fixup function for 4xx PCI bridges by determining if the bridge is
compatible with 440EPx/GRx.  The flag is checked in the indirect_write_config
function, and forces any writes to the PCI_CACHE_LINE_SIZE register to be
zero, which will disable MRMs for these chips.

A similar workaround has been tested by AMCC on various PCI cards, such as
the Silicon Image ATA card and Intel E1000 GIGE card.  Hangs were seen with
the Silicon Image card, and MRMs were seen on the bus with a PCI analyzer.
With the workaround in place, the card functioned properly and only Memory
Reads were seen on the bus with the analyzer.

Acked-by: Stefan Roese &lt;sr@denx.de&gt;
Signed-off-by: Josh Boyer &lt;jwboyer@linux.vnet.ibm.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The 440EPx/GRx chips don't support PCI MRM commands.  Drivers determine this
by looking for a zero value in the PCI cache line size register.  However,
some drivers write to this register upon initialization.  This can cause
MRMs to be used on these chips, which may cause deadlocks on PLB4.

The workaround implemented here introduces a new indirect_type flag, called
PPC_INDIRECT_TYPE_BROKEN_MRM.  This is set in the pci_controller structure in
the pci fixup function for 4xx PCI bridges by determining if the bridge is
compatible with 440EPx/GRx.  The flag is checked in the indirect_write_config
function, and forces any writes to the PCI_CACHE_LINE_SIZE register to be
zero, which will disable MRMs for these chips.

A similar workaround has been tested by AMCC on various PCI cards, such as
the Silicon Image ATA card and Intel E1000 GIGE card.  Hangs were seen with
the Silicon Image card, and MRMs were seen on the bus with a PCI analyzer.
With the workaround in place, the card functioned properly and only Memory
Reads were seen on the bus with the analyzer.

Acked-by: Stefan Roese &lt;sr@denx.de&gt;
Signed-off-by: Josh Boyer &lt;jwboyer@linux.vnet.ibm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[POWERPC] PCI: Add 64-bit physical address support to setup_indirect_pci</title>
<updated>2007-10-12T04:05:17+00:00</updated>
<author>
<name>Valentine Barshak</name>
<email>vbarshak@ru.mvista.com</email>
</author>
<published>2007-10-08T12:51:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=d94bad827d9a0df939a0e7ed081a2780b9f72c4b'/>
<id>d94bad827d9a0df939a0e7ed081a2780b9f72c4b</id>
<content type='text'>
Add 64-bit physical address support to setup_indirect_pci().

Signed-off-by: Valentine Barshak &lt;vbarshak@ru.mvista.com&gt;
Acked-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
Signed-off-by: Paul Mackerras &lt;paulus@samba.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add 64-bit physical address support to setup_indirect_pci().

Signed-off-by: Valentine Barshak &lt;vbarshak@ru.mvista.com&gt;
Acked-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
Signed-off-by: Paul Mackerras &lt;paulus@samba.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[POWERPC] indirect_pci_ops: Use named structure member initializers</title>
<updated>2007-08-17T01:01:54+00:00</updated>
<author>
<name>Nathan Lynch</name>
<email>ntl@pobox.com</email>
</author>
<published>2007-08-09T19:18:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=c78d453b6f95ff38a2226f6f77a4b08a6e27fc42'/>
<id>c78d453b6f95ff38a2226f6f77a4b08a6e27fc42</id>
<content type='text'>
Signed-off-by: Nathan Lynch &lt;ntl@pobox.com&gt;
Signed-off-by: Paul Mackerras &lt;paulus@samba.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Signed-off-by: Nathan Lynch &lt;ntl@pobox.com&gt;
Signed-off-by: Paul Mackerras &lt;paulus@samba.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[POWERPC] Fix PCI indirect for big-endian cfg_addr</title>
<updated>2007-07-25T05:29:53+00:00</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2007-07-25T05:29:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=7659c038d3d0a635b5aeff04aed523d7b6c1dde8'/>
<id>7659c038d3d0a635b5aeff04aed523d7b6c1dde8</id>
<content type='text'>
We didn't actually propogate the flag we pass into setup_indirect_pci()
to set indirect_type and thus were getting the wrong endianness if
PPC_INDIRECT_TYPE_BIG_ENDIAN was set.

Also, we need to or in additional flags rather than just doing a
direct assignment.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
We didn't actually propogate the flag we pass into setup_indirect_pci()
to set indirect_type and thus were getting the wrong endianness if
PPC_INDIRECT_TYPE_BIG_ENDIAN was set.

Also, we need to or in additional flags rather than just doing a
direct assignment.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[POWERPC] Make endianess of cfg_addr for indirect pci ops runtime</title>
<updated>2007-07-24T03:29:09+00:00</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2007-07-19T21:07:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=2e56ff206b7c6c28b847ccdbe46ad69b3263ac32'/>
<id>2e56ff206b7c6c28b847ccdbe46ad69b3263ac32</id>
<content type='text'>
Make it so we do a runtime check to know if we need to write cfg_addr
as big or little endian.  This is needed if we want to allow 86xx support
to co-exist in the same kernel as other 6xx PPCs.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Make it so we do a runtime check to know if we need to write cfg_addr
as big or little endian.  This is needed if we want to allow 86xx support
to co-exist in the same kernel as other 6xx PPCs.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[POWERPC] Removed setup_indirect_pci_nomap</title>
<updated>2007-07-23T15:27:08+00:00</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2007-07-19T20:44:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=d5269966e57484548bc5d38e117f161bf2f56ce9'/>
<id>d5269966e57484548bc5d38e117f161bf2f56ce9</id>
<content type='text'>
We don't use setup_indirect_pci_nomap in arch/powerpc and it appears
the users that needed it from arch/ppc are now using setup_indirect_pci.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
We don't use setup_indirect_pci_nomap in arch/powerpc and it appears
the users that needed it from arch/ppc are now using setup_indirect_pci.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[POWERPC] Added indirect quirk to handle PCIe PHB that have issue w/no link</title>
<updated>2007-07-23T15:27:07+00:00</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2007-07-11T18:22:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=62c66c8e55fae40d93d8f79d60e2ed50379e46f9'/>
<id>62c66c8e55fae40d93d8f79d60e2ed50379e46f9</id>
<content type='text'>
Added PPC_INDIRECT_TYPE_NO_PCIE_LINK flag to the indirect pci handling
code to ensure that we don't talk to any device other than the PHB
if we don't have PCIe link.  Some controllers will lockup if they try
to do a config cycle to any device on the bus except the PHB.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Added PPC_INDIRECT_TYPE_NO_PCIE_LINK flag to the indirect pci handling
code to ensure that we don't talk to any device other than the PHB
if we don't have PCIe link.  Some controllers will lockup if they try
to do a config cycle to any device on the bus except the PHB.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[POWERPC] 86xx: Workaround PCI_PRIMARY_BUS usage</title>
<updated>2007-06-29T06:58:24+00:00</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2007-06-26T17:12:55+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=476f5779b77a919f0ced5953de2bf3e0f2d02c07'/>
<id>476f5779b77a919f0ced5953de2bf3e0f2d02c07</id>
<content type='text'>
The Freescale PCI-e controllers have an issue in that they use the
PCI_PRIMARY_BUS register in the virtual P2P bridge to determine which
bus number to match on when generating a type 0 config cycle.  The
issue is if we are renumbering bus numbers to match Linux we will try
setting the PCI_PRIMARY_BUS and will not know which bus number to use
for generating type 0 config cycles.  We surpress writing the register
in the P2P bridge and always keep it at zero.

In the future when proper PCI domain support is working we should be
able to remove this.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The Freescale PCI-e controllers have an issue in that they use the
PCI_PRIMARY_BUS register in the virtual P2P bridge to determine which
bus number to match on when generating a type 0 config cycle.  The
issue is if we are renumbering bus numbers to match Linux we will try
setting the PCI_PRIMARY_BUS and will not know which bus number to use
for generating type 0 config cycles.  We surpress writing the register
in the P2P bridge and always keep it at zero.

In the future when proper PCI domain support is working we should be
able to remove this.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
