linux-toradex.git/arch/ppc/kernel/head_44x.S, branch v2.6.24-rc2

[PPC] Use cpu setup routines from cpu_setup_44x.S for ARCH=ppc

2007-10-04T01:02:09+00:00

Commit 8112753bb2c0045398c89d0647792b39805f6d40 made 44x in
ARCH=powerpc builds use cpu setup routines in cpu_setup_44x.S,
but didn't make a similar change for ARCH=ppc, and consequently
the ARCH=ppc builds fail with undefined symbols (since both use
the same cputable.c).

This fixes it by including cpu_setup_44x.S in the ARCH=ppc builds,
and by taking out the now-redundant FPU initialization in
arch/ppc/kernel/head_44x.S.

Signed-off-by: Paul Mackerras

Remove obsolete #include

2006-06-30T17:25:36+00:00

Signed-off-by: Jörn Engel 
Signed-off-by: Adrian Bunk

[PATCH] powerpc: trivial: modify comments to refer to new location of files

2006-02-10T05:53:51+00:00

This patch removes all self references and fixes references to files
in the now defunct arch/ppc64 tree.  I think this accomplises
everything wanted, though there might be a few references I missed.

Signed-off-by: Jon Mason 
Signed-off-by: Paul Mackerras

[PATCH] ppc32: Allow ERPN for early serial to depend on CPU type

2005-11-07T15:53:26+00:00

The PowerPC 440SPe supports up to 16 GB of RAM, and therefore its IO registers
are at 0x4_xxxx_xxxx instead of being at 0x1_xxxx_xxxx like most other PPC 440
chips.  To allow for this, this patch moves the definition of the ERPN used
for mapping UART0 from being hard-coded in the head_44x.S assembly code to
being defined in ibm44x.h.

Signed-off-by: Roland Dreier 
Signed-off-by: Matt Porter 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

[PATCH] ppc32: replace use of _GLOBAL with .globl for ppc32

2005-10-19T23:43:34+00:00

The _GLOBAL() macro is for text symbols only. Changed to using
.globl for .data symbols.  This is also needed in ppc32 land
to allow FSL Book-E, 40x, and 44x to work.

Signed-off-by: Kumar K. Gala 
Signed-off-by: Paul Mackerras

powerpc: merge idle_power4.S and trapc.s

2005-10-01T08:43:42+00:00

Use idle_power4.S from ppc64 as we are not going to support
32 bit power4 in the merged tree.

Merge ppc64 traps.c into powerpc traps.c:
	use ppc64 versions of exception routine names
		(as they don't have StudlyCaps)
	make all the versions if die() have the same
		prototype

Signed-off-by: Stephen Rothwell

kbuild: m68k,parisc,ppc,ppc64,s390,xtensa use generic asm-offsets.h support

2005-09-09T18:57:26+00:00

Delete obsoleted parts form arch makefiles and rename to asm-offsets.h

Signed-off-by: Sam Ravnborg

[PATCH] ppc32: Added support for the Book-E style Watchdog Timer

2005-09-05T07:05:56+00:00

PowerPC 40x and Book-E processors support a watchdog timer at the processor
core level.  The timer has implementation dependent timeout frequencies
that can be configured by software.

One the first Watchdog timeout we get a critical exception.  It is left to
board specific code to determine what should happen at this point.  If
nothing is done and another timeout period expires the processor may
attempt to reset the machine.

Command line parameters:
  wdt=0 : disable watchdog (default)
  wdt=1 : enable watchdog

  wdt_period=N : N sets the value of the Watchdog Timer Period.

  The Watchdog Timer Period meaning is implementation specific. Check
  User Manual for the processor for more details.

This patch is based off of work done by Takeharu Kato.

Signed-off-by: Matt McClintock 
Signed-off-by: Kumar Gala 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

[PATCH] ppc32: add 440ep support

2005-08-02T02:14:01+00:00

Add PPC440EP core support.  PPC440EP is a PPC440-based SoC with a classic PPC
FPU and another set of peripherals.

Signed-off-by: Wade Farnsworth 
Signed-off-by: Matt Porter 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

[PATCH] ppc32: fix 44x early serial debug for configurations with more than 512M of RAM

2005-07-30T17:14:46+00:00

Fix 44x early serial debugging for big RAM configurations (more than 512M).
 We cannot use default OpenBIOS virtual mapping, because it interferes with
pinned TLB entry.

While we are at it, move early UART mapping to TLB slot 0, so it can
survive longer during boot process (slot 1 is used by the first ioremap
call, effectively killing UART mapping if it occupies this slot).  Also,
change UART TLB entry size to 4K (256M is too much for a bunch of registers
:).  Squash some warnings on the way.

Tested on Ebony and Ocotea with 1G of RAM.

Thanks to Scott Coulter  for diagnosing this
problem.

Signed-off-by: Eugene Surovegin 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds