linux-toradex.git/arch/ppc/mm, branch master

powerpc: Remove arch/ppc and include/asm-ppc

2008-06-10T11:40:22+00:00

All the maintained platforms are now in arch/powerpc, so the old
arch/ppc stuff can now go away.

Acked-by: Adrian Bunk 
Acked-by: Arnd Bergmann 
Acked-by: Becky Bruce 
Acked-by: Benjamin Herrenschmidt 
Acked-by: Geert Uytterhoeven 
Acked-by: Grant Likely 
Acked-by: Jochen Friedrich 
Acked-by: John Linn 
Acked-by: Jon Loeliger 
Acked-by: Josh Boyer 
Acked-by: Kumar Gala 
Acked-by: Olof Johansson 
Acked-by: Peter Korsgaard 
Acked-by: Scott Wood 
Acked-by: Sean MacLennan 
Acked-by: Segher Boessenkool 
Acked-by: Stefan Roese 
Acked-by: Stephen Neuendorffer 
Acked-by: Wolfgang Denk 
Signed-off-by: Paul Mackerras

[POWERPC] ppc: Remove redundant display of free swap space in show_mem()

2008-04-01T09:45:16+00:00

show_mem() has no need to print the amount of free swap space manually
because show_free_areas() does this already and is called by the
former.

The two outputs only differ in text formatting:

  printk("Free swap  = %lukB\n", ...);
  printk("Free swap:       %6ldkB\n", ...);

Signed-off-by: Johannes Weiner 
Cc: Benjamin Herrenschmidt 
Signed-off-by: Andrew Morton 
Signed-off-by: Paul Mackerras

CONFIG_HIGHPTE vs. sub-page page tables.

2008-02-08T17:22:42+00:00

Background: I've implemented 1K/2K page tables for s390.  These sub-page
page tables are required to properly support the s390 virtualization
instruction with KVM.  The SIE instruction requires that the page tables
have 256 page table entries (pte) followed by 256 page status table entries
(pgste).  The pgstes are only required if the process is using the SIE
instruction.  The pgstes are updated by the hardware and by the hypervisor
for a number of reasons, one of them is dirty and reference bit tracking.
To avoid wasting memory the standard pte table allocation should return
1K/2K (31/64 bit) and 2K/4K if the process is using SIE.

Problem: Page size on s390 is 4K, page table size is 1K or 2K.  That means
the s390 version for pte_alloc_one cannot return a pointer to a struct
page.  Trouble is that with the CONFIG_HIGHPTE feature on x86 pte_alloc_one
cannot return a pointer to a pte either, since that would require more than
32 bit for the return value of pte_alloc_one (and the pte * would not be
accessible since its not kmapped).

Solution: The only solution I found to this dilemma is a new typedef: a
pgtable_t.  For s390 pgtable_t will be a (pte *) - to be introduced with a
later patch.  For everybody else it will be a (struct page *).  The
additional problem with the initialization of the ptl lock and the
NR_PAGETABLE accounting is solved with a constructor pgtable_page_ctor and
a destructor pgtable_page_dtor.  The page table allocation and free
functions need to call these two whenever a page table page is allocated or
freed.  pmd_populate will get a pgtable_t instead of a struct page pointer.
 To get the pgtable_t back from a pmd entry that has been installed with
pmd_populate a new function pmd_pgtable is added.  It replaces the pmd_page
call in free_pte_range and apply_to_pte_range.

Signed-off-by: Martin Schwidefsky 
Cc: 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

add mm argument to pte/pmd/pud/pgd_free

2008-02-05T17:44:18+00:00

(with Martin Schwidefsky )

The pgd/pud/pmd/pte page table allocation functions get a mm_struct pointer as
first argument.  The free functions do not get the mm_struct argument.  This
is 1) asymmetrical and 2) to do mm related page table allocations the mm
argument is needed on the free function as well.

[kamalesh@linux.vnet.ibm.com: i386 fix]
[akpm@linux-foundation.org: coding-syle fixes]
Signed-off-by: Benjamin Herrenschmidt 
Signed-off-by: Martin Schwidefsky 
Cc: 
Signed-off-by: Kamalesh Babulal 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

[PPC] Remove 85xx from arch/ppc

2008-01-28T14:33:10+00:00

85xx exists in arch/powerpc as well as cuImage support to boot from
a u-boot that doesn't support device trees.

Signed-off-by: Kumar Gala

[PPC] Remove 83xx from arch/ppc

2008-01-28T14:33:09+00:00

83xx exists in arch/powerpc as well as cuImage support to boot from
a u-boot that doesn't support device trees.

Signed-off-by: Kumar Gala

[POWERPC] 4xx: Fix TLB 0 problem with CONFIG_SERIAL_TEXT_DEBUG

2007-12-23T19:31:16+00:00

Right now TLB entry 0 ist used as UART0 mapping for the early debug
output (via CONFIG_SERIAL_TEXT_DEBUG). This causes problems when many
TLB's get used upon Linux bootup (e.g. while PCIe scanning behind
bridges and/or switches on 440SPe platforms). This will overwrite the
TLB 0 entry and further debug output's may crash/hang the system.

This patch moves the early debug UART0 TLB entry from 0 to 62 as done
in arch/powerpc. This way it is in the "pinned" area and will not get
overwritten. Also the arch/ppc/mm/44x_mmu.c code is now synced with the
newer code from arch/powerpc.

Signed-off-by: Stefan Roese 
Signed-off-by: Josh Boyer

[POWERPC] Fix 8xx build breakage due to _tlbie changes

2007-11-20T07:42:00+00:00

My changes to _tlbie to fix 4xx unfortunately broke 8xx build in a
couple of places.  This fixes it.

Spotted by Olof Johansson.

Signed-off-by: Benjamin Herrenschmidt 
Signed-off-by: Vitaly Bordug 
Signed-off-by: Paul Mackerras

[POWERPC] ppc405 Fix arithmatic rollover bug when memory size under 16M

2007-11-01T12:15:59+00:00

mmu_mapin_ram() loops over total_lowmem to setup page tables.  However, if
total_lowmem is less that 16M, the subtraction rolls over and results in
a number just under 4G (because total_lowmem is an unsigned value).

This patch rejigs the loop from countup to countdown to eliminate the
bug.

Special thanks to Magnus Hjorth who wrote the original patch to fix this
bug.  This patch improves on his by making the loop code simpler (which
also eliminates the possibility of another rollover at the high end)
and also applies the change to arch/powerpc.

Signed-off-by: Grant Likely 
Signed-off-by: Josh Boyer

[POWERPC] 4xx: Deal with 44x virtually tagged icache

2007-11-01T12:15:30+00:00

The 44x family has an interesting "feature" which is a virtually
tagged instruction cache (yuck !). So far, we haven't dealt with
it properly, which means we've been mostly lucky or people didn't
report the problems, unless people have been running custom patches
in their distro...

This is an attempt at fixing it properly. I chose to do it by
setting a global flag whenever we change a PTE that was previously
marked executable, and flush the entire instruction cache upon
return to user space when that happens.

This is a bit heavy handed, but it's hard to do more fine grained
flushes as the icbi instruction, on those processor, for some very
strange reasons (since the cache is virtually mapped) still requires
a valid TLB entry for reading in the target address space, which
isn't something I want to deal with.

Signed-off-by: Benjamin Herrenschmidt 
Signed-off-by: Josh Boyer