linux-toradex.git/arch/riscv/kernel/entry.S, branch v4.19

RISC-V: implement low-level interrupt handling

2018-08-13T15:31:31+00:00

Add support for a routine that dispatches exceptions with the interrupt
flags set to either the IPI or irqdomain code (and the clock source in the
future).

Loosely based on the irq-riscv-int.c irqchip driver from the RISC-V tree.

Signed-off-by: Christoph Hellwig 
Signed-off-by: Palmer Dabbelt

RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER handler

2018-03-14T20:46:29+00:00

The existing mechanism for handling IRQs on RISC-V is pretty ugly: the irq
entry code selects the handler via Kconfig dependencies.

Use the new generic IRQ handling infastructure, which allows boot time
registration of the low level entry handler.

This does add an additional load to the interrupt latency, but there's a
lot of tuning left to be done there on RISC-V so it's OK for now.

Signed-off-by: Palmer Dabbelt 
Signed-off-by: Thomas Gleixner 
Reviewed-by: Christoph Hellwig 
Acked-by: Stafford Horne 
Cc: jonas@southpole.se
Cc: catalin.marinas@arm.com
Cc: Will Deacon 
Cc: linux@armlinux.org.uk
Cc: stefan.kristiansson@saunalahti.fi
Cc: openrisc@lists.librecores.org
Cc: linux-riscv@lists.infradead.org
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lkml.kernel.org/r/20180307235731.22627-3-palmer@sifive.com

RISC-V: Enable IRQ during exception handling

2018-02-20T18:56:14+00:00

Interrupt is allowed during exception handling.
There are warning messages if the kernel enables the configuration
'CONFIG_DEBUG_ATOMIC_SLEEP=y'.

BUG: sleeping function called from invalid context at kernel/locking/rwsem.c:23
in_atomic(): 0, irqs_disabled(): 1, pid: 43, name: ash
CPU: 0 PID: 43 Comm: ash Tainted:  G	 W	 4.15.0-rc8-00089-g89ffdae-dirty #17
Call Trace:
[<000000009abb1587>] walk_stackframe+0x0/0x7a
[<00000000d4f3d088>] ___might_sleep+0x102/0x11a
[<00000000b1fd792a>] down_read+0x18/0x28
[<000000000289ec01>] do_page_fault+0x86/0x2f6
[<00000000012441f6>] _do_fork+0x1b4/0x1e0
[<00000000f46c3e3b>] ret_from_syscall+0xa/0xe

Reviewed-by: Christoph Hellwig 
Signed-off-by: Zong Li 
Signed-off-by: Palmer Dabbelt 
Signed-off-by: Palmer Dabbelt

riscv: disable SUM in the exception handler

2018-01-31T03:12:38+00:00

The SUM bit is enabled at the beginning of the copy_{to,from}_user and
{get,put}_user routines, and cleared before they return.  But these user
copy helper can be interrupted by exceptions, in which case the SUM bit
will remain set, which leads to elevated privileges for the code running
in exception context, as that can now access userspace address space
unconditionally.  This frequently happens when the user copy routines
access freshly allocated user memory that hasn't been faulted in, and a
pagefault needs to be taken before the user copy routines can continue.

Fix this by unconditionally clearing SUM when the exception handler is
called - the restore code will automatically restore it based on the
saved value.

Signed-off-by: Christoph Hellwig 
Signed-off-by: Palmer Dabbelt

riscv: rename SR_* constants to match the spec

2018-01-07T23:14:39+00:00

Signed-off-by: Christoph Hellwig 
Signed-off-by: Palmer Dabbelt

RISC-V: Task implementation

2017-09-26T22:26:46+00:00

This patch contains the implementation of tasks on RISC-V, most of which
is involved in task switching.

Signed-off-by: Palmer Dabbelt