linux-toradex.git/arch/riscv/kernel/smpboot.c, branch v4.20

RISC-V: Use Linux logical CPU number instead of hartid

2018-10-23T00:03:37+00:00

Setup the cpu_logical_map during boot. Moreover, every SBI call
and PLIC context are based on the physical hartid. Use the logical
CPU to hartid mapping to pass correct hartid to respective functions.

Signed-off-by: Atish Patra 
Reviewed-by: Anup Patel 
Reviewed-by: Christoph Hellwig 
Signed-off-by: Palmer Dabbelt

RISC-V: Use WRITE_ONCE instead of direct access

2018-10-23T00:03:37+00:00

The secondary harts spin on couple of per cpu variables until both of
these are non-zero so it's not necessary to have any ordering here.
However, WRITE_ONCE should be used to avoid tearing.

Signed-off-by: Atish Patra 
Reviewed-by: Christoph Hellwig 
Signed-off-by: Palmer Dabbelt

RISC-V: Use mmgrab()

2018-10-23T00:03:36+00:00

commit f1f1007644ff ("mm: add new mmgrab() helper") added a
helper that we missed out on.

Signed-off-by: Palmer Dabbelt 
Reviewed-by: Christoph Hellwig 
Signed-off-by: Atish Patra 
Signed-off-by: Palmer Dabbelt

RISC-V: Rename im_okay_therefore_i_am to found_boot_cpu

2018-10-23T00:03:36+00:00

The old name was a bit odd.

Signed-off-by: Palmer Dabbelt 
Signed-off-by: Atish Patra 
Reviewed-by: Christoph Hellwig 
Signed-off-by: Palmer Dabbelt

RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartid

2018-10-23T00:03:36+00:00

It's a bit confusing exactly what this function does: it actually
returns the hartid of an OF processor node, failing with -1 on invalid
nodes.  I've changed the name to _hartid() in order to make that a bit
more clear, as well as adding a comment.

Signed-off-by: Palmer Dabbelt 
[Atish: code comment formatting update]
Signed-off-by: Atish Patra 
Reviewed-by: Christoph Hellwig 
Signed-off-by: Palmer Dabbelt

RISC-V: Disable preemption before enabling interrupts

2018-10-23T00:03:36+00:00

Currently, irq is enabled before preemption disabling happens.
If the scheduler fired right here and cpu is scheduled then it
may blow up.

Signed-off-by: Palmer Dabbelt 
[Atish: Commit text and code comment formatting update]
Signed-off-by: Atish Patra 
Reviewed-by: Christoph Hellwig 
Signed-off-by: Palmer Dabbelt

RISC-V: Comment on the TLB flush in smp_callin()

2018-10-23T00:03:36+00:00

This isn't readily apparent from reading the code.

Signed-off-by: Palmer Dabbelt 
[Atish: code comment formatting update]
Signed-off-by: Atish Patra 
Reviewed-by: Christoph Hellwig 
Signed-off-by: Palmer Dabbelt

clocksource: new RISC-V SBI timer driver

2018-08-13T15:31:31+00:00

The RISC-V ISA defines a per-hart real-time clock and timer, which is
present on all systems.  The clock is accessed via the 'rdtime'
pseudo-instruction (which reads a CSR), and the timer is set via an SBI
call.

Contains various improvements from Atish Patra .

Signed-off-by: Dmitriy Cherkasov 
Signed-off-by: Palmer Dabbelt 
[hch: remove dead code, add SPDX tags, used riscv_of_processor_hart(),
 minor cleanups, merged  hotplug cpu support and other improvements
 from Atish]
Signed-off-by: Christoph Hellwig 
Acked-by: Thomas Gleixner 
Reviewed-by: Atish Patra 
Signed-off-by: Palmer Dabbelt

RISC-V: Init and Halt Code

2017-09-26T22:26:44+00:00

This contains the various __init C functions, the initial assembly
kernel entry point, and the code to reset the system.  When a file was
init-related this patch contains the entire file.

Signed-off-by: Palmer Dabbelt