linux-toradex.git/arch/sh/kernel/cpu/sh2/entry.S, branch v6.3 Linux kernel for Apalis and Colibri modules sh: sh2: convert to SPDX identifiers 2018-12-28T20:11:45+00:00 Kuninori Morimoto kuninori.morimoto.gx@renesas.com 2018-12-28T08:31:56+00:00 47d11326259baaed7659b47e3a49d31715719793 Update license to use SPDX-License-Identifier instead of verbose license text. Link: http://lkml.kernel.org/r/87efawcszk.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Cc: Rich Felker <dalias@libc.org> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> 
Update license to use SPDX-License-Identifier instead of verbose license
text.

Link: http://lkml.kernel.org/r/87efawcszk.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Cc: Rich Felker <dalias@libc.org>
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
sh: SMP support for SH2 entry.S 2016-08-05T03:29:37+00:00 Rich Felker dalias@libc.org 2016-02-15T18:32:31+00:00 4b6ef05b3e89f5bdb888fbd5467e996a9193b884 The SH2 version of entry.S uses global variables, which need to be cpu-local in order to work with SMP. For ease of access from asm, simply use arrays indexed by cpu number, and require the availability of an address (mmio register or properly setup per-cpu memory) from which the current cpu's index can be read. Signed-off-by: Rich Felker <dalias@libc.org> 
The SH2 version of entry.S uses global variables, which need to be
cpu-local in order to work with SMP. For ease of access from asm,
simply use arrays indexed by cpu number, and require the availability
of an address (mmio register or properly setup per-cpu memory) from
which the current cpu's index can be read.

Signed-off-by: Rich Felker <dalias@libc.org>
sh: add support for J-Core J2 processor 2016-08-05T03:29:31+00:00 Rich Felker dalias@libc.org 2016-03-17T23:09:37+00:00 5a846abad07f6f30adfa3e46c5c7a47d2e7b1e63 At the CPU/ISA level, the J2 is compatible with SH-2, and thus the changes to add J2 support build on existing SH-2 support. However, J2 does not duplicate the memory-mapped SH-2 features like the cache interface. Instead, the cache interfaces is described in the device tree, and new code is added to be able to access the flat device tree at early boot before it is unflattened. Support is also added for receiving interrupts on trap numbers in the range 16 to 31, since the J-Core aic1 interrupt controller generates these traps. This range was unused but nominally for hardware exceptions on SH-2, and a few values in this range were used for exceptions on SH-2A, but SH-2A has its own version of the relevant code. No individual cpu subtypes are added for J2 since the intent moving forward is to represent SoCs with device tree rather than as hard-coded subtypes in the kernel. The CPU_SUBTYPE_J2 Kconfig item exists only to fit into the existing cpu selection mechanism until it is overhauled. Signed-off-by: Rich Felker <dalias@libc.org> 
At the CPU/ISA level, the J2 is compatible with SH-2, and thus the
changes to add J2 support build on existing SH-2 support. However, J2
does not duplicate the memory-mapped SH-2 features like the cache
interface. Instead, the cache interfaces is described in the device
tree, and new code is added to be able to access the flat device tree
at early boot before it is unflattened.

Support is also added for receiving interrupts on trap numbers in the
range 16 to 31, since the J-Core aic1 interrupt controller generates
these traps. This range was unused but nominally for hardware
exceptions on SH-2, and a few values in this range were used for
exceptions on SH-2A, but SH-2A has its own version of the relevant
code.

No individual cpu subtypes are added for J2 since the intent moving
forward is to represent SoCs with device tree rather than as
hard-coded subtypes in the kernel. The CPU_SUBTYPE_J2 Kconfig item
exists only to fit into the existing cpu selection mechanism until it
is overhauled.

Signed-off-by: Rich Felker <dalias@libc.org>
sh: provide unified syscall trap compatible with all SH models 2016-03-17T19:46:06+00:00 Rich Felker dalias@libc.org 2015-12-17T01:04:25+00:00 3623d138213aedf0e2c89720f6a3cd0e164cb310 Historically SH-2 Linux (and originally uClinux) used a syscall calling convention incompatible with the established SH-3/4 Linux ABI. This choice was made because the trap range used by the existing ABI, 0x10-0x17, overlaps with the hardware exception/interrupt trap range reserved by SH-2, and in particular, with the SH-2A divide-by-zero and division-overflow exceptions. Despite the documented syscall convention using the low bits of the trap number to signal the number of arguments the kernel should expect, no version of the kernel has ever used this information, nor is it useful; all of the registers need to be saved anyway. Therefore, it is possible to pick a new trap number, 0x1f, that is both supported by all existing SH-3/4 kernels and unassigned as a hardware trap in the SH-2 range. This makes it possible to produce SH-2 application binaries that are forwards-compatible with running on SH-3/4 kernels and to treat SH as a unified platform with varying ISA support levels rather than multiple gratuitously-incompatible platforms. This patch adjusts the range checking SH-2 and SH-2A kernels make for the syscall trap to accept the range 0x1f-0x2f rather than just 0x20-0x2f. As a result, trap 0x1f now acts as a syscall for all SH models. Signed-off-by: Rich Felker <dalias@libc.org> 
Historically SH-2 Linux (and originally uClinux) used a syscall
calling convention incompatible with the established SH-3/4 Linux ABI.
This choice was made because the trap range used by the existing ABI,
0x10-0x17, overlaps with the hardware exception/interrupt trap range
reserved by SH-2, and in particular, with the SH-2A divide-by-zero and
division-overflow exceptions.

Despite the documented syscall convention using the low bits of the
trap number to signal the number of arguments the kernel should
expect, no version of the kernel has ever used this information, nor
is it useful; all of the registers need to be saved anyway. Therefore,
it is possible to pick a new trap number, 0x1f, that is both supported
by all existing SH-3/4 kernels and unassigned as a hardware trap in
the SH-2 range. This makes it possible to produce SH-2 application
binaries that are forwards-compatible with running on SH-3/4 kernels
and to treat SH as a unified platform with varying ISA support levels
rather than multiple gratuitously-incompatible platforms.

This patch adjusts the range checking SH-2 and SH-2A kernels make for
the syscall trap to accept the range 0x1f-0x2f rather than just
0x20-0x2f. As a result, trap 0x1f now acts as a syscall for all SH
models.

Signed-off-by: Rich Felker <dalias@libc.org>
sh: Make sure rte delay slots are nopped out on all parts. 2009-08-14T22:41:45+00:00 Paul Mundt lethal@linux-sh.org 2009-08-14T22:41:45+00:00 7a90e00dda0bae66b5232d5a37155f13a0581369 Future SH parts do not support any instruction but a nop in the rte delay slot, so make the change for all offending parts. SH-5 is excluded from this, and already has its own set of restrictions with regards to rte delay slot handling. Signed-off-by: Paul Mundt <lethal@linux-sh.org> 
Future SH parts do not support any instruction but a nop in the rte delay
slot, so make the change for all offending parts. SH-5 is excluded from
this, and already has its own set of restrictions with regards to rte
delay slot handling.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
sh: migrate to arch/sh/include/ 2008-07-28T23:09:44+00:00 Paul Mundt lethal@linux-sh.org 2008-07-28T23:09:44+00:00 f15cbe6f1a4b4d9df59142fc8e4abb973302cf44 This follows the sparc changes a439fe51a1f8eb087c22dd24d69cebae4a3addac. Most of the moving about was done with Sam's directions at: http://marc.info/?l=linux-sh&m=121724823706062&w=2 with subsequent hacking and fixups entirely my fault. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org> 
This follows the sparc changes a439fe51a1f8eb087c22dd24d69cebae4a3addac.

Most of the moving about was done with Sam's directions at:

http://marc.info/?l=linux-sh&m=121724823706062&w=2

with subsequent hacking and fixups entirely my fault.

Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
sh2(A) exception handler update 2008-07-28T09:10:34+00:00 Yoshinori Sato ysato@users.sourceforge.jp 2008-07-09T16:20:03+00:00 6e80f5e8c4c685eb7bc34c3916e3d986b03f9981 This patch is By sh2 - Remove duplicate code - Reduce stack usage - Cleanup and little optimize By sh2a - Add missing handler(256 to 511) - Use sh2a instructions handler Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org> 
This patch is

By sh2
- Remove duplicate code
- Reduce stack usage
- Cleanup and little optimize

By sh2a
- Add missing handler(256 to 511)
- Use sh2a instructions handler

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
sh: Fix up the address error exception handler for SH-2. 2008-03-13T10:43:07+00:00 Kieran Bingham kbingham@mpc-data.co.uk 2008-03-13T10:43:07+00:00 6c0602b8dd4b41c078b52ed8ea97023970781744 Presently the SH-2/SH-2A address error exception dispatch copies off the register state from the stack and skips over the first register, skewing the rest. Fix up the math here so that the proper register state is handed down to the exception handler itself. Signed-off-by: Kieran Bingham <kbingham@mpc-data.co.uk> Signed-off-by: Paul Mundt <lethal@linux-sh.org> 
Presently the SH-2/SH-2A address error exception dispatch copies off the
register state from the stack and skips over the first register, skewing
the rest. Fix up the math here so that the proper register state is
handed down to the exception handler itself.

Signed-off-by: Kieran Bingham <kbingham@mpc-data.co.uk>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
sh: SH-2A FPU support. 2008-01-28T04:18:57+00:00 Paul Mundt lethal@linux-sh.org 2007-11-26T11:38:36+00:00 74d99a5e262229ee865f6f68528d10b82471ead6 Signed-off-by: Kieran Bingham <kbingham@mpc-data.co.uk> Signed-off-by: Paul Mundt <lethal@linux-sh.org> 
Signed-off-by: Kieran Bingham <kbingham@mpc-data.co.uk>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
sh: Share bug/debug traps across _32 and _64. 2008-01-28T04:18:50+00:00 Paul Mundt lethal@linux-sh.org 2007-11-20T09:08:06+00:00 5a4f7c66be981c6b5f44a4d66a14ea6ac9b7b6b0 Signed-off-by: Paul Mundt <lethal@linux-sh.org> 
Signed-off-by: Paul Mundt <lethal@linux-sh.org>