<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-toradex.git/arch/sh/kernel/head_32.S, branch v4.19</title>
<subtitle>Linux kernel for Apalis and Colibri modules</subtitle>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/'/>
<entry>
<title>sh: fix build regression with CONFIG_OF &amp;&amp; !CONFIG_OF_FLATTREE</title>
<updated>2016-07-31T03:33:32+00:00</updated>
<author>
<name>Rich Felker</name>
<email>dalias@libc.org</email>
</author>
<published>2016-06-01T22:21:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=03767daa1387f87619404bfe108ebb6aa5826e00'/>
<id>03767daa1387f87619404bfe108ebb6aa5826e00</id>
<content type='text'>
Such a configuration could only be selected by manually selecting
CONFIG_OF; SH_DEVICE_TREE selects both. The affected code is using the
flat DTB at boot time and thus rightfully should depend on
OF_FLATTREE, not just OF.

Signed-off-by: Rich Felker &lt;dalias@libc.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Such a configuration could only be selected by manually selecting
CONFIG_OF; SH_DEVICE_TREE selects both. The affected code is using the
flat DTB at boot time and thus rightfully should depend on
OF_FLATTREE, not just OF.

Signed-off-by: Rich Felker &lt;dalias@libc.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sh: add device tree support and generic board using device tree</title>
<updated>2016-03-17T19:46:11+00:00</updated>
<author>
<name>Rich Felker</name>
<email>dalias@libc.org</email>
</author>
<published>2016-01-23T00:45:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=7480e0aabd5f9e6c3e3b72ed206e89284e90f11f'/>
<id>7480e0aabd5f9e6c3e3b72ed206e89284e90f11f</id>
<content type='text'>
Add a new pseudo-board, within the existing SH boards/machine-vectors
framework, which does not represent any actual hardware but instead
requires all hardware to be described by the device tree blob provided
by the boot loader. Changes made are thus non-invasive and do not risk
breaking support for legacy boards.

New hardware, including the open-hardware J2 and associated SoC
devices, will use device free from the outset. Legacy SH boards can
transition to device tree once all their hardware has device tree
bindings, driver support for device tree, and a dts file for the
board.

It is intented that, once all boards are supported in the new
framework, the existing machine-vectors framework should be removed
and the new device tree setup code integrated directly.

Signed-off-by: Rich Felker &lt;dalias@libc.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add a new pseudo-board, within the existing SH boards/machine-vectors
framework, which does not represent any actual hardware but instead
requires all hardware to be described by the device tree blob provided
by the boot loader. Changes made are thus non-invasive and do not risk
breaking support for legacy boards.

New hardware, including the open-hardware J2 and associated SoC
devices, will use device free from the outset. Legacy SH boards can
transition to device tree once all their hardware has device tree
bindings, driver support for device tree, and a dts file for the
board.

It is intented that, once all boards are supported in the new
framework, the existing machine-vectors framework should be removed
and the new device tree setup code integrated directly.

Signed-off-by: Rich Felker &lt;dalias@libc.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sh: boot kernel with SR.BL set</title>
<updated>2010-09-30T00:43:32+00:00</updated>
<author>
<name>Magnus Damm</name>
<email>damm@opensource.se</email>
</author>
<published>2010-09-24T09:05:38+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=68a1aed7039e5a94a8e60e23fdf676738c36086a'/>
<id>68a1aed7039e5a94a8e60e23fdf676738c36086a</id>
<content type='text'>
Update the SH kernel to keep SR.BL set until the VBR
register has been initialized. Useful to allow boot
of the kernel even though exceptions are pending.

Without this patch there is a window of time when
exceptions such as NMI are enabled but no exception
handlers are installed.

This patch modifies both the zImage loader and the
actual kernel to boot with BL=1, but the zImage
loader is modfied in such a way that the init_sr
value is unchanged to not break the zImage loader
provided by kexec.

Tested on sh7724 Ecovec and on the SH4AL-DSP core
included in sh7372.

Signed-off-by: Magnus Damm &lt;damm@opensource.se&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Update the SH kernel to keep SR.BL set until the VBR
register has been initialized. Useful to allow boot
of the kernel even though exceptions are pending.

Without this patch there is a window of time when
exceptions such as NMI are enabled but no exception
handlers are installed.

This patch modifies both the zImage loader and the
actual kernel to boot with BL=1, but the zImage
loader is modfied in such a way that the init_sr
value is unchanged to not break the zImage loader
provided by kexec.

Tested on sh7724 Ecovec and on the SH4AL-DSP core
included in sh7372.

Signed-off-by: Magnus Damm &lt;damm@opensource.se&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sh: Use correct mask when comparing PMB DATA array values</title>
<updated>2010-04-25T19:44:23+00:00</updated>
<author>
<name>Matt Fleming</name>
<email>matt@console-pimps.org</email>
</author>
<published>2010-04-25T19:18:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=035ca59fe8399a67b56511bd5b28130f0c4874a0'/>
<id>035ca59fe8399a67b56511bd5b28130f0c4874a0</id>
<content type='text'>
Previously we were masking the PMB DATA array values with the value of
__MEMORY_START | PMB_V, which misses some PFN bits off the mask.

Signed-off-by: Matt Fleming &lt;matt@console-pimps.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Previously we were masking the PMB DATA array values with the value of
__MEMORY_START | PMB_V, which misses some PFN bits off the mask.

Signed-off-by: Matt Fleming &lt;matt@console-pimps.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sh: __cpuinit annotate the CPU init path.</title>
<updated>2010-04-21T03:20:42+00:00</updated>
<author>
<name>Paul Mundt</name>
<email>lethal@linux-sh.org</email>
</author>
<published>2010-04-21T03:20:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=4a6feab0ee5240c4bd5378d9f8a46b85718c68a7'/>
<id>4a6feab0ee5240c4bd5378d9f8a46b85718c68a7</id>
<content type='text'>
All of the regular CPU init path needs to be __cpuinit annotated for CPU
hotplug.

Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
All of the regular CPU init path needs to be __cpuinit annotated for CPU
hotplug.

Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sh: Merge legacy and dynamic PMB modes.</title>
<updated>2010-02-18T09:13:51+00:00</updated>
<author>
<name>Paul Mundt</name>
<email>lethal@linux-sh.org</email>
</author>
<published>2010-02-18T09:13:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=d01447b3197c2c470a14666be2c640407bbbfec7'/>
<id>d01447b3197c2c470a14666be2c640407bbbfec7</id>
<content type='text'>
This implements a bit of rework for the PMB code, which permits us to
kill off the legacy PMB mode completely. Rather than trusting the boot
loader to do the right thing, we do a quick verification of the PMB
contents to determine whether to have the kernel setup the initial
mappings or whether it needs to mangle them later on instead.

If we're booting from legacy mappings, the kernel will now take control
of them and make them match the kernel's initial mapping configuration.
This is accomplished by breaking the initialization phase out in to
multiple steps: synchronization, merging, and resizing. With the recent
rework, the synchronization code establishes page links for compound
mappings already, so we build on top of this for promoting mappings and
reclaiming unused slots.

At the same time, the changes introduced for the uncached helpers also
permit us to dynamically resize the uncached mapping without any
particular headaches. The smallest page size is more than sufficient for
mapping all of kernel text, and as we're careful not to jump to any far
off locations in the setup code the mapping can safely be resized
regardless of whether we are executing from it or not.

Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This implements a bit of rework for the PMB code, which permits us to
kill off the legacy PMB mode completely. Rather than trusting the boot
loader to do the right thing, we do a quick verification of the PMB
contents to determine whether to have the kernel setup the initial
mappings or whether it needs to mangle them later on instead.

If we're booting from legacy mappings, the kernel will now take control
of them and make them match the kernel's initial mapping configuration.
This is accomplished by breaking the initialization phase out in to
multiple steps: synchronization, merging, and resizing. With the recent
rework, the synchronization code establishes page links for compound
mappings already, so we build on top of this for promoting mappings and
reclaiming unused slots.

At the same time, the changes introduced for the uncached helpers also
permit us to dynamically resize the uncached mapping without any
particular headaches. The smallest page size is more than sufficient for
mapping all of kernel text, and as we're careful not to jump to any far
off locations in the setup code the mapping can safely be resized
regardless of whether we are executing from it or not.

Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sh: uncached mapping helpers.</title>
<updated>2010-02-17T07:28:00+00:00</updated>
<author>
<name>Paul Mundt</name>
<email>lethal@linux-sh.org</email>
</author>
<published>2010-02-17T07:28:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=9edef28653a519bf0a48250f36cce96b1736ec4e'/>
<id>9edef28653a519bf0a48250f36cce96b1736ec4e</id>
<content type='text'>
This adds some helper routines for uncached mapping support. This
simplifies some of the cases where we need to check the uncached mapping
boundaries in addition to giving us a centralized location for building
more complex manipulation on top of.

Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This adds some helper routines for uncached mapping support. This
simplifies some of the cases where we need to check the uncached mapping
boundaries in addition to giving us a centralized location for building
more complex manipulation on top of.

Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sh: PMB tidying.</title>
<updated>2010-02-17T06:33:30+00:00</updated>
<author>
<name>Paul Mundt</name>
<email>lethal@linux-sh.org</email>
</author>
<published>2010-02-17T06:33:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=51becfd96287b3913b13075699433730984e2f4f'/>
<id>51becfd96287b3913b13075699433730984e2f4f</id>
<content type='text'>
Some overdue cleanup of the PMB code, killing off unused functionality
and duplication sprinkled about the tree.

Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Some overdue cleanup of the PMB code, killing off unused functionality
and duplication sprinkled about the tree.

Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sh: Track the uncached mapping size.</title>
<updated>2010-01-21T06:54:31+00:00</updated>
<author>
<name>Paul Mundt</name>
<email>lethal@linux-sh.org</email>
</author>
<published>2010-01-21T06:54:31+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=3125ee72dca25fc2157dcddd07e2d740db921fc4'/>
<id>3125ee72dca25fc2157dcddd07e2d740db921fc4</id>
<content type='text'>
This provides a variable for tracking the uncached mapping size, and uses
it for pretty printing the uncached lowmem range. Beyond this, we'll also
be building on top of this for figuring out from where the remainder of
P2 becomes usable when constructing unrelated mappings.

Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This provides a variable for tracking the uncached mapping size, and uses
it for pretty printing the uncached lowmem range. Beyond this, we'll also
be building on top of this for figuring out from where the remainder of
P2 becomes usable when constructing unrelated mappings.

Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sh: Rework P2 to only include kernel text.</title>
<updated>2010-01-21T06:42:58+00:00</updated>
<author>
<name>Paul Mundt</name>
<email>lethal@linux-sh.org</email>
</author>
<published>2010-01-21T06:42:58+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=2023b843d7b62d99e7356b872e99abc7d6667e49'/>
<id>2023b843d7b62d99e7356b872e99abc7d6667e49</id>
<content type='text'>
This effectively neutralizes P2 by getting rid of P1 identity mapping
for all available memory and instead only establishes a single unbuffered
PMB entry (16MB -- the smallest available) that covers the kernel.

As using segmentation for abusing caching attributes in drivers is no
longer supported (and there are no drivers that can be enabled in 32-bit
mode that do this), this provides us with all of the uncached access
needs by the kernel itself.

Drivers and their ilk need to specify their caching attributes when
remapping through page tables, as usual.

Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This effectively neutralizes P2 by getting rid of P1 identity mapping
for all available memory and instead only establishes a single unbuffered
PMB entry (16MB -- the smallest available) that covers the kernel.

As using segmentation for abusing caching attributes in drivers is no
longer supported (and there are no drivers that can be enabled in 32-bit
mode that do this), this provides us with all of the uncached access
needs by the kernel itself.

Drivers and their ilk need to specify their caching attributes when
remapping through page tables, as usual.

Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
