linux-toradex.git/arch/sparc/kernel/pcr.c, branch v3.14.42

sparc64: T5 PMU

2014-10-30T16:38:27+00:00

The T5 (niagara5) has different PCR related HV fast trap values and a new
HV API Group. This patch utilizes these and shares when possible with niagara4.

We use the same sparc_pmu niagara4_pmu. Should there be new effort to
obtain the MCU perf statistics then this would have to be changed.

Cc: sparclinux@vger.kernel.org
Signed-off-by: Bob Picco 
Signed-off-by: David S. Miller 
Signed-off-by: Greg Kroah-Hartman

sparc64: Add PCR ops for SPARC-T4.

2012-08-19T06:26:19+00:00

This is enough to get the NMIs working, more work is needed
for perf events.

Signed-off-by: David S. Miller

sparc64: Abstract away the %pcr values used to enable/disable NMI

2012-08-19T06:26:19+00:00

We assumed PCR_PIC_PRIV can always be used to disable it, but that
won't be true for SPARC-T4.

This allows us also to get rid of some messy defines used in only
one location.

Signed-off-by: David S. Miller

sparc64: Abstract away the NMI PIC counter computation.

2012-08-19T06:26:18+00:00

Signed-off-by: David S. Miller

sparc64: Abstract away PIC register accesses.

2012-08-19T06:26:14+00:00

And, like for the PCR, allow indexing of different PIC register
numbers.

This also removes all of the non-__KERNEL__ bits from asm/perfctr.h,
nothing kernel side should include it any more.

Signed-off-by: David S. Miller

sparc64: Add 'reg_num' argument to pcr_ops methods.

2012-08-19T06:04:08+00:00

SPARC-T4 and later have multiple PCR registers, one for each
PIC counter.

Signed-off-by: David S. Miller

Disintegrate asm/system.h for Sparc

2012-03-28T17:30:03+00:00

Disintegrate asm/system.h for Sparc.

Signed-off-by: David Howells 
cc: sparclinux@vger.kernel.org

sparc: move symbol exporters to use export.h not module.h

2011-10-31T23:30:53+00:00

Many of the core sparc kernel files are not modules, but just
including module.h for exporting symbols.  Now these files can
use the lighter footprint export.h for this role.

Signed-off-by: Paul Gortmaker

sparc: fix implicit use of spitfire.h in pcr.c and of_device_64.c

2011-10-31T23:30:51+00:00

To resolve these on 64bit allnoconfig builds:

  CC      arch/sparc/kernel/pcr.o
arch/sparc/kernel/pcr.c: In function 'register_perf_hsvc':
arch/sparc/kernel/pcr.c:102: error: 'tlb_type' undeclared (first use in this function)

  CC      arch/sparc/kernel/of_device_64.o
arch/sparc/kernel/of_device_64.c: In function 'build_device_resources':
arch/sparc/kernel/of_device_64.c:406: error: 'tlb_type' undeclared (first use in this function)

Signed-off-by: Paul Gortmaker

sparc: Detect and handle UltraSPARC-T3 cpu types.

2011-07-28T05:10:10+00:00

The cpu compatible string we look for is "SPARC-T3".

As far as memset/memcpy optimizations go, we treat this chip the same
as Niagara-T2/T2+.  Use cache initializing stores for memset, and use
perfetch, FPU block loads, cache initializing stores, and block stores
for copies.

We use the Niagara-T2 perf support, since T3 is a close relative in
this regard.  Later we'll add support for the new events T3 can
report, plus enable T3's new "sample" mode.

For now I haven't added any new ELF hwcap flags.  We probably need
to add a couple, for example:

T2 and T3 both support the population count instruction in hardware.

T3 supports VIS3 instructions, including support (finally) for
partitioned shift.  One can also now move directly between float
and integer registers.

T3 supports instructions meant to help with Galois Field and other HPC
calculations, such as XOR multiply.  Also there are "OP and negate"
instructions, for example "fnmul" which is multiply-and-negate.

T3 recognizes the transactional memory opcodes, however since
transactional memory isn't supported: 1) 'commit' behaves as a NOP and
2) 'chkpt' always branches 3) 'rdcps' returns all zeros and 4) 'wrcps'
behaves as a NOP.

So we'll need about 3 new elf capability flags in the end to represent
all of these things.

Signed-off-by: David S. Miller