linux-toradex.git/arch/sparc/kernel/perf_event.c, branch v3.0.91

sparc64: Fix bit twiddling in sparc_pmu_enable_event().

2012-10-28T17:02:13+00:00

[ Upstream commit e793d8c6740f8fe704fa216e95685f4d92c4c4b9 ]

There was a serious disconnect in the logic happening in
sparc_pmu_disable_event() vs. sparc_pmu_enable_event().

Event disable is implemented by programming a NOP event into the PCR.

However, event enable was not reversing this operation.  Instead, it
was setting the User/Priv/Hypervisor trace enable bits.

That's not sparc_pmu_enable_event()'s job, that's what
sparc_pmu_enable() and sparc_pmu_disable() do .

The intent of sparc_pmu_enable_event() is clear, since it first clear
out the event type encoding field.  So fix this by OR'ing in the event
encoding rather than the trace enable bits.

Signed-off-by: David S. Miller 
Signed-off-by: Greg Kroah-Hartman

sparc64: Like x86 we should check current->mm during perf backtrace generation.

2012-10-28T17:02:13+00:00

[ Upstream commit 08280e6c4c2e8049ac61d9e8e3536ec1df629c0d ]

If the MM is not active, only report the top-level PC.  Do not try to
access the address space.

Signed-off-by: David S. Miller 
Signed-off-by: Greg Kroah-Hartman

sparc: Detect and handle UltraSPARC-T3 cpu types.

2011-08-16T01:31:40+00:00

[ Upstream commit 4ba991d3eb379fbaa22049e7002341e97a673685 ]

The cpu compatible string we look for is "SPARC-T3".

As far as memset/memcpy optimizations go, we treat this chip the same
as Niagara-T2/T2+.  Use cache initializing stores for memset, and use
perfetch, FPU block loads, cache initializing stores, and block stores
for copies.

We use the Niagara-T2 perf support, since T3 is a close relative in
this regard.  Later we'll add support for the new events T3 can
report, plus enable T3's new "sample" mode.

For now I haven't added any new ELF hwcap flags.  We probably need
to add a couple, for example:

T2 and T3 both support the population count instruction in hardware.

T3 supports VIS3 instructions, including support (finally) for
partitioned shift.  One can also now move directly between float
and integer registers.

T3 supports instructions meant to help with Galois Field and other HPC
calculations, such as XOR multiply.  Also there are "OP and negate"
instructions, for example "fnmul" which is multiply-and-negate.

T3 recognizes the transactional memory opcodes, however since
transactional memory isn't supported: 1) 'commit' behaves as a NOP and
2) 'chkpt' always branches 3) 'rdcps' returns all zeros and 4) 'wrcps'
behaves as a NOP.

So we'll need about 3 new elf capability flags in the end to represent
all of these things.

Signed-off-by: David S. Miller 
Signed-off-by: Greg Kroah-Hartman

sparc: consolidate show_cpuinfo in cpu.c

2011-04-21T22:45:45+00:00

We have all the cpu related info in cpu.c - so move
the remaining functions to support /proc/cpuinfo to this file.

Signed-off-by: Sam Ravnborg 
Signed-off-by: David S. Miller

Fix common misspellings

2011-03-31T14:26:23+00:00

Fixes generated by 'codespell' and manually reviewed.

Signed-off-by: Lucas De Marchi

perf: Dynamic pmu types

2010-12-16T10:36:43+00:00

Extend the perf_pmu_register() interface to allow for named and
dynamic pmu types.

Because we need to support the existing static types we cannot use
dynamic types for everything, hence provide a type argument.

If we want to enumerate the PMUs they need a name, provide one.

Signed-off-by: Peter Zijlstra 
LKML-Reference: <20101117222056.259707703@chello.nl>
Signed-off-by: Ingo Molnar

perf, sparc: Fix CONFIG_PERF_EVENTS=y build error

2010-12-09T23:29:24+00:00

Fix a typo in:

  004417a6d468: perf, arch: Cleanup perf-pmu init vs lockup-detector

Which caused a build failure on Sparc, reported by Stephen Rothwell.

Reported-by: Stephen Rothwell 
Cc: David S. Miller 
Signed-off-by: Peter Zijlstra 
Signed-off-by: Ingo Molnar

perf, arch: Cleanup perf-pmu init vs lockup-detector

2010-11-26T14:14:56+00:00

The perf hardware pmu got initialized at various points in the boot,
some before early_initcall() some after (notably arch_initcall).

The problem is that the NMI lockup detector is ran from early_initcall()
and expects the hardware pmu to be present.

Sanitize this by moving all architecture hardware pmu implementations to
initialize at early_initcall() and move the lockup detector to an explicit
initcall right after that.

Cc: paulus 
Cc: davem 
Cc: Michael Cree 
Cc: Deng-Cheng Zhu 
Acked-by: Paul Mundt 
Acked-by: Will Deacon 
Signed-off-by: Peter Zijlstra 
LKML-Reference: <1290707759.2145.119.camel@laptop>
Signed-off-by: Ingo Molnar

Merge branch 'linus' into perf/core

2010-09-23T06:02:09+00:00

Conflicts:
	arch/sparc/kernel/perf_event.c

Merge reason: Resolve the conflict.

Signed-off-by: Ingo Molnar

sparc64: Support RAW perf events.

2010-09-13T00:20:24+00:00

Encoding is "(encoding << 16) | pic_mask"

Signed-off-by: David S. Miller