linux-toradex.git/arch/sparc, branch v3.1

sparc: Add alignment flag to PCI expansion resources

2011-10-19T23:20:50+00:00

Currently no type of alignment is specified for PCI expansion roms while 
parsing the openfirmware tree. This causes calls to pci_map_rom() to fail.
IORESOURCE_SIZEALIGN is the default alignment used for rom resouces in 
pci/probe.c, and has been verified to work with various cards on a ultra 10.

Signed-off-By: Kjetil Oftedal 
Signed-off-by: David S. Miller

sparc: Avoid calling sigprocmask()

2011-10-12T19:27:35+00:00

Use set_current_blocked() instead.

Signed-off-by: David S. Miller

sparc: Use set_current_blocked()

2011-10-12T19:25:28+00:00

As described in e6fa16ab ("signal: sigprocmask() should do
retarget_shared_pending()") the modification of current->blocked is
incorrect as we need to check whether the signal we're about to block
is pending in the shared queue.

Cc: Oleg Nesterov 
Cc: "David S. Miller" 
Signed-off-by: Matt Fleming 
Signed-off-by: David S. Miller

sparc32,leon: SRMMU MMU Table probe fix

2011-10-07T19:08:01+00:00

The LEON MMU Model (SRMMU) does not implement MMu Table probing
in hardware, instead it is implemented in software. However the
software implementation does not return the PTE as it should which
always results in INVALID entires and the PROM mappings are not
inherited as they should during startup. The following patch
removes the masking of the PTE.

Signed-off-by: Daniel Hellstrom 
Signed-off-by: David S. Miller

sparc64: Force the execute bit in OpenFirmware's translation entries.

2011-09-29T19:18:59+00:00

In the OF 'translations' property, the template TTEs in the mappings
never specify the executable bit.  This is the case even though some
of these mappings are for OF's code segment.

Therefore, we need to force the execute bit on in every mapping.

This problem can only really trigger on Niagara/sun4v machines and the
history behind this is a little complicated.

Previous to sun4v, the sun4u TTE entries lacked a hardware execute
permission bit.  So OF didn't have to ever worry about setting
anything to handle executable pages.  Any valid TTE loaded into the
I-TLB would be respected by the chip.

But sun4v Niagara chips have a real hardware enforced executable bit
in their TTEs.  So it has to be set or else the I-TLB throws an
instruction access exception with type code 6 (protection violation).

We've been extremely fortunate to not get bitten by this in the past.

The best I can tell is that the OF's mappings for it's executable code
were mapped using permanent locked mappings on sun4v in the past.
Therefore, the fact that we didn't have the exec bit set in the OF
translations we would use did not matter in practice.

Thanks to Greg Onufer for helping me track this down.

Signed-off-by: David S. Miller

sparc: Make '-p' boot option meaningful again.

2011-09-21T19:48:06+00:00

If "-p" is given on the command line, clear the CON_BOOT
flag for the initial early boot PROM console.

This is necessary to try and see crash messages that occur
between the registry of the VT console and the probing of
the first framebuffer or serial console.  During this time
no console messages are emitted because the VT console
registry (even if no backend is registered to it) removes
the early console if CON_BOOT is set.

Signed-off-by: David S. Miller

sparc, exec: remove redundant addr_limit assignment

2011-09-21T06:12:42+00:00

The address limit is already set in flush_old_exec() so this assignment of
USER_DS is redundant.

Signed-off-by: Mathias Krause 
Cc: David Miller 
Signed-off-by: Andrew Morton 
Signed-off-by: David S. Miller

sparc64: Future proof Niagara cpu detection.

2011-09-16T21:21:33+00:00

Recognize T4 and T5 chips.  Treating them both as "T2 plus other
stuff" should be extremely safe and make sure distributions will work
when those chips actually ship to customers.

Signed-off-by: David S. Miller

sparc64: Only Panther cheetah+ chips have POPC.

2011-08-30T04:14:29+00:00

Signed-off-by: David S. Miller

sparc32,sun4d: Change IPI IRQ level to prevent collision between IPI and timer interrupt

2011-08-29T16:20:40+00:00

On Sun4d systems running in SMP mode, IRQ 14 is used for timer interrupts
and has a specialized interrupt handler. IPI is currently set to use IRQ 14
as well, which causes it to trigger the timer interrupt handler, and not the
IPI interrupt handler.

The IPI interrupt is therefore changed to IRQ 13, which is the highest
normally handled interrupt. This IRQ is also used for SBUS interrupts,
however there is nothing in the IPI/SBUS interrupt handlers that indicate
that they will not handle sharing the interrupt.
(IRQ 13 is indicated as audio interrupt, which is unlikely to be found in a
sun4d system)

Signed-off-by: Kjetil Oftedal 
Signed-off-by: David S. Miller