linux-toradex.git/arch/x86/kernel/cpu/cyrix.c, branch v3.2 Linux kernel for Apalis and Colibri modules x86, cpu: mv display_cacheinfo -> cpu_detect_cache_sizes 2009-11-23T19:59:53+00:00 Borislav Petkov petkovbb@googlemail.com 2009-11-21T13:01:45+00:00 27c13ecec4d8856687b50b959e1146845b478f95 display_cacheinfo() doesn't display anything anymore and it is used to detect CPU cache sizes. Rename it accordingly. Signed-off-by: Borislav Petkov <petkovbb@gmail.com> LKML-Reference: <20091121130145.GA31357@liondog.tnic> Signed-off-by: H. Peter Anvin <hpa@zytor.com> 
display_cacheinfo() doesn't display anything anymore and it is used to
detect CPU cache sizes. Rename it accordingly.

Signed-off-by: Borislav Petkov <petkovbb@gmail.com>
LKML-Reference: <20091121130145.GA31357@liondog.tnic>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
x86/cpu: Clean up various files a bit 2009-07-11T09:24:09+00:00 Alan Cox alan@linux.intel.com 2009-07-03T23:35:45+00:00 8bdbd962ecfcbdd96f9dbb02d780b4553afd2543 No code changes except printk levels (although some of the K6 mtrr code might be clearer if there were a few as would splitting out some of the intel cache code). Signed-off-by: Alan Cox <alan@linux.intel.com> LKML-Reference: <new-submission> Signed-off-by: Ingo Molnar <mingo@elte.hu> 
No code changes except printk levels (although some of the K6
mtrr code might be clearer if there were a few as would
splitting out some of the intel cache code).

Signed-off-by: Alan Cox <alan@linux.intel.com>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
x86: move various CPU initialization objects into .cpuinit.rodata 2009-03-12T12:13:07+00:00 Jan Beulich jbeulich@novell.com 2009-03-12T12:08:49+00:00 02dde8b45c5460794b9052d7c12939fe3eb63c2c Impact: debuggability and micro-optimization Putting whatever is possible into the (final) .rodata section increases the likelihood of catching memory corruption bugs early, and reduces false cache line sharing. Signed-off-by: Jan Beulich <jbeulich@novell.com> LKML-Reference: <49B90961.76E4.0078.0@novell.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> 
Impact: debuggability and micro-optimization

Putting whatever is possible into the (final) .rodata section increases
the likelihood of catching memory corruption bugs early, and reduces
false cache line sharing.

Signed-off-by: Jan Beulich <jbeulich@novell.com>
LKML-Reference: <49B90961.76E4.0078.0@novell.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
x86: remove duplicated get_model_name() calling 2008-09-06T12:09:12+00:00 Yinghai Lu yhlu.kernel@gmail.com 2008-09-06T08:52:27+00:00 1b05d60d60e81c6594da8298107a05b506f01797 Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> 
Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
x86: remove cpu_vendor_dev 2008-09-04T19:09:45+00:00 Yinghai Lu yhlu.kernel@gmail.com 2008-09-04T19:09:45+00:00 10a434fcb23a57c385177a0086955fae01003f64 1. add c_x86_vendor into cpu_dev 2. change cpu_devs to static 3. check c_x86_vendor before put that cpu_dev into array 4. remove alignment for 64bit 5. order the sequence in cpu_devs according to link sequence... so could put intel at first, then amd... Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> 
1. add c_x86_vendor into cpu_dev
2. change cpu_devs to static
3. check c_x86_vendor before put that cpu_dev into array
4. remove alignment for 64bit
5. order the sequence in cpu_devs according to link sequence...
   so could put intel at first, then amd...

Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
x86: move mtrr cpu cap setting early in early_init_xxxx 2008-09-04T19:09:43+00:00 Yinghai Lu yhlu.kernel@gmail.com 2008-09-04T19:09:43+00:00 5fef55fddb7317585cabc1eae38dbd57f1c59729 Krzysztof Helt found MTRR is not detected on k6-2 root cause: we moved mtrr_bp_init() early for mtrr trimming, and in early_detect we only read the CPU capability from cpuid, so some cpu doesn't have that bit in cpuid. So we need to add early_init_xxxx to preset those bit before mtrr_bp_init for those earlier cpus. this patch is for v2.6.27 Reported-by: Krzysztof Helt <krzysztof.h1@wp.pl> Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> 
Krzysztof Helt found MTRR is not detected on k6-2

root cause:
	we moved mtrr_bp_init() early for mtrr trimming,
and in early_detect we only read the CPU capability from cpuid,
so some cpu doesn't have that bit in cpuid.

So we need to add early_init_xxxx to preset those bit before mtrr_bp_init
for those earlier cpus.

this patch is for v2.6.27

Reported-by: Krzysztof Helt <krzysztof.h1@wp.pl>
Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Merge branch 'x86/urgent' into x86/cpu 2008-08-28T02:17:07+00:00 H. Peter Anvin hpa@zytor.com 2008-08-28T02:17:07+00:00 b30a72a7edfc64c8929104d5c2178aca489aa559 Conflicts: arch/x86/kernel/cpu/cyrix.c 
Conflicts:

	arch/x86/kernel/cpu/cyrix.c
x86: fix "kernel won't boot on a Cyrix MediaGXm (Geode)" 2008-08-20T09:31:00+00:00 Samuel Sieb samuel@sieb.net 2008-08-07T05:06:29+00:00 c6744955d0ec0cb485c28c51eeb7185e260f6172 Cyrix MediaGXm/Cx5530 Unicorn Revision 1.19.3B has stopped booting starting at v2.6.22. The reason is this commit: > commit f25f64ed5bd3c2932493681bdfdb483ea707da0a > Author: Juergen Beisert <juergen@kreuzholzen.de> > Date: Sun Jul 22 11:12:38 2007 +0200 > > x86: Replace NSC/Cyrix specific chipset access macros by inlined functions. this commit activated a macro which was dormant before due to (buggy) macro side-effects. I've looked through various datasheets and found that the GXm and GXLV Geode processors don't have an incrementor. Remove the incrementor setup entirely. As the incrementor value differs according to clock speed and we would hope that the BIOS configures it correctly, it is probably the right solution. Cc: <stable@kernel.org> Signed-off-by: Ingo Molnar <mingo@elte.hu> 
Cyrix MediaGXm/Cx5530 Unicorn Revision 1.19.3B has stopped
booting starting at v2.6.22.

The reason is this commit:

> commit f25f64ed5bd3c2932493681bdfdb483ea707da0a
> Author: Juergen Beisert <juergen@kreuzholzen.de>
> Date:   Sun Jul 22 11:12:38 2007 +0200
>
>     x86: Replace NSC/Cyrix specific chipset access macros by inlined functions.

this commit activated a macro which was dormant before due to (buggy)
macro side-effects.

I've looked through various datasheets and found that the GXm and GXLV
Geode processors don't have an incrementor.

Remove the incrementor setup entirely.  As the incrementor value
differs according to clock speed and we would hope that the BIOS
configures it correctly, it is probably the right solution.

Cc: <stable@kernel.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
x86, cyrix: debug 2008-07-22T10:24:00+00:00 Ingo Molnar mingo@elte.hu 2008-07-22T09:58:14+00:00 026e2c05ef58ef413e2d52696f125d5ea1aa8bce Signed-off-by: Ingo Molnar <mingo@elte.hu> 
Signed-off-by: Ingo Molnar <mingo@elte.hu>
x86: clean up cpu capabilities accesses, cyrix.c 2008-04-17T15:40:51+00:00 Ingo Molnar mingo@elte.hu 2008-02-26T07:52:27+00:00 1d007cd5aeea2c9283e01433dbce4c9f91dd7823 Signed-off-by: Ingo Molnar <mingo@elte.hu> 
Signed-off-by: Ingo Molnar <mingo@elte.hu>