linux-toradex.git/arch/x86/kernel/cpu/mcheck, branch master

x86/mce: Streamline MCE subsystem's naming

2018-12-05T17:00:29+00:00

Rename the containing folder to "mce" which is the most widespread name.
Drop the "mce[-_]" filename prefix of some compilation units (while
others don't have it).

This unifies the file naming in the MCE subsystem:

mce/
|-- amd.c
|-- apei.c
|-- core.c
|-- dev-mcelog.c
|-- genpool.c
|-- inject.c
|-- intel.c
|-- internal.h
|-- Makefile
|-- p5.c
|-- severity.c
|-- therm_throt.c
|-- threshold.c
`-- winchip.c

No functional changes.

Signed-off-by: Borislav Petkov 
Reviewed-by: Ingo Molnar 
Acked-by: Tony Luck 
Link: https://lkml.kernel.org/r/20181205141323.14995-1-bp@alien8.de

x86/MCE/AMD: Fix the thresholding machinery initialization order

2018-11-28T09:10:36+00:00

Currently, the code sets up the thresholding interrupt vector and only
then goes about initializing the thresholding banks. Which is wrong,
because an early thresholding interrupt would cause a NULL pointer
dereference when accessing those banks and prevent the machine from
booting.

Therefore, set the thresholding interrupt vector only *after* having
initialized the banks successfully.

Fixes: 18807ddb7f88 ("x86/mce/AMD: Reset Threshold Limit after logging error")
Reported-by: Rafał Miłecki 
Reported-by: John Clemens 
Signed-off-by: Borislav Petkov 
Tested-by: Rafał Miłecki 
Tested-by: John Clemens 
Cc: Aravind Gopalakrishnan 
Cc: linux-edac@vger.kernel.org
Cc: stable@vger.kernel.org
Cc: Tony Luck 
Cc: x86@kernel.org
Cc: Yazen Ghannam 
Link: https://lkml.kernel.org/r/20181127101700.2964-1-zajec5@gmail.com
Link: https://bugzilla.kernel.org/show_bug.cgi?id=201291

acpi/nfit, x86/mce: Validate a MCE's address before using it

2018-11-06T18:13:26+00:00

The NFIT machine check handler uses the physical address from the mce
structure, and compares it against information in the ACPI NFIT table
to determine whether that location lies on an NVDIMM. The mce->addr
field however may not always be valid, and this is indicated by the
MCI_STATUS_ADDRV bit in the status field.

Export mce_usable_address() which already performs validation for the
address, and use it in the NFIT handler.

Fixes: 6839a6d96f4e ("nfit: do an ARS scrub on hitting a latent media error")
Reported-by: Robert Elliott 
Signed-off-by: Vishal Verma 
Signed-off-by: Borislav Petkov 
CC: Arnd Bergmann 
Cc: Dan Williams 
CC: Dave Jiang 
CC: elliott@hpe.com
CC: "H. Peter Anvin" 
CC: Ingo Molnar 
CC: Len Brown 
CC: linux-acpi@vger.kernel.org
CC: linux-edac 
CC: linux-nvdimm@lists.01.org
CC: Qiuxu Zhuo 
CC: "Rafael J. Wysocki" 
CC: Ross Zwisler 
CC: stable 
CC: Thomas Gleixner 
CC: Tony Luck 
CC: x86-ml 
CC: Yazen Ghannam 
Link: http://lkml.kernel.org/r/20181026003729.8420-2-vishal.l.verma@intel.com

acpi/nfit, x86/mce: Handle only uncorrectable machine checks

2018-11-06T18:13:10+00:00

The MCE handler for nfit devices is called for memory errors on a
Non-Volatile DIMM and adds the error location to a 'badblocks' list.
This list is used by the various NVDIMM drivers to avoid consuming known
poison locations during IO.

The MCE handler gets called for both corrected and uncorrectable errors.
Until now, both kinds of errors have been added to the badblocks list.
However, corrected memory errors indicate that the problem has already
been fixed by hardware, and the resulting interrupt is merely a
notification to Linux.

As far as future accesses to that location are concerned, it is
perfectly fine to use, and thus doesn't need to be included in the above
badblocks list.

Add a check in the nfit MCE handler to filter out corrected mce events,
and only process uncorrectable errors.

Fixes: 6839a6d96f4e ("nfit: do an ARS scrub on hitting a latent media error")
Reported-by: Omar Avelar 
Signed-off-by: Vishal Verma 
Signed-off-by: Borislav Petkov 
CC: Arnd Bergmann 
CC: Dan Williams 
CC: Dave Jiang 
CC: elliott@hpe.com
CC: "H. Peter Anvin" 
CC: Ingo Molnar 
CC: Len Brown 
CC: linux-acpi@vger.kernel.org
CC: linux-edac 
CC: linux-nvdimm@lists.01.org
CC: Qiuxu Zhuo 
CC: "Rafael J. Wysocki" 
CC: Ross Zwisler 
CC: stable 
CC: Thomas Gleixner 
CC: Tony Luck 
CC: x86-ml 
CC: Yazen Ghannam 
Link: http://lkml.kernel.org/r/20181026003729.8420-1-vishal.l.verma@intel.com

x86: Clean up 'sizeof x' => 'sizeof(x)'

2018-10-29T06:13:28+00:00

"sizeof(x)" is the canonical coding style used in arch/x86 most of the time.
Fix the few places that didn't follow the convention.

(Also do some whitespace cleanups in a few places while at it.)

[ mingo: Rewrote the changelog. ]

Signed-off-by: Jordan Borgner 
Cc: Borislav Petkov 
Cc: H. Peter Anvin 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Link: http://lkml.kernel.org/r/20181028125828.7rgammkgzep2wpam@JordanDesktop
Signed-off-by: Ingo Molnar

Merge branch 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

2018-10-23T15:16:40+00:00

Pull x86 cpu updates from Ingo Molnar:
 "The main changes in this cycle were:

   - Add support for the "Dhyana" x86 CPUs by Hygon: these are licensed
     based on the AMD Zen architecture, and are built and sold in China,
     for domestic datacenter use. The code is pretty close to AMD
     support, mostly with a few quirks and enumeration differences. (Pu
     Wen)

   - Enable CPUID support on Cyrix 6x86/6x86L processors"

* 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  tools/cpupower: Add Hygon Dhyana support
  cpufreq: Add Hygon Dhyana support
  ACPI: Add Hygon Dhyana support
  x86/xen: Add Hygon Dhyana support to Xen
  x86/kvm: Add Hygon Dhyana support to KVM
  x86/mce: Add Hygon Dhyana support to the MCA infrastructure
  x86/bugs: Add Hygon Dhyana to the respective mitigation machinery
  x86/apic: Add Hygon Dhyana support
  x86/pci, x86/amd_nb: Add Hygon Dhyana support to PCI and northbridge
  x86/amd_nb: Check vendor in AMD-only functions
  x86/alternative: Init ideal_nops for Hygon Dhyana
  x86/events: Add Hygon Dhyana support to PMU infrastructure
  x86/smpboot: Do not use BSP INIT delay and MWAIT to idle on Dhyana
  x86/cpu/mtrr: Support TOP_MEM2 and get MTRR number
  x86/cpu: Get cache info and setup cache cpumap for Hygon Dhyana
  x86/cpu: Create Hygon Dhyana architecture support file
  x86/CPU: Change query logic so CPUID is enabled before testing
  x86/CPU: Use correct macros for Cyrix calls

Merge branch 'ras-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

2018-10-23T12:46:36+00:00

Pull RAS updates from Ingo Molnar:
 "Misc smaller fixes and cleanups"

* 'ras-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/mcelog: Remove one mce_helper definition
  x86/mce: Add macros for the corrected error count bit field
  x86/mce: Use BIT_ULL(x) for bit mask definitions
  x86/mce-inject: Reset injection struct after injection

x86/mcelog: Remove one mce_helper definition

2018-10-17T22:05:04+00:00

Commit

  5de97c9f6d85f ("x86/mce: Factor out and deprecate the /dev/mcelog driver")

moved the old interface into one file including mce_helper definition as
static and "extern". Remove one.

Fixes: 5de97c9f6d85f ("x86/mce: Factor out and deprecate the /dev/mcelog driver")
Signed-off-by: Sebastian Andrzej Siewior 
Signed-off-by: Borislav Petkov 
CC: "H. Peter Anvin" 
CC: Ingo Molnar 
CC: Thomas Gleixner 
CC: Tony Luck 
CC: linux-edac 
CC: x86-ml 
Link: http://lkml.kernel.org/r/20181017170554.18841-3-bigeasy@linutronix.de

x86/mce: Add Hygon Dhyana support to the MCA infrastructure

2018-09-27T16:28:59+00:00

The machine check architecture for Hygon Dhyana CPU is similar to the
AMD family 17h one. Add vendor checking for Hygon Dhyana to share the
code path of AMD family 17h.

Signed-off-by: Pu Wen 
Signed-off-by: Borislav Petkov 
Reviewed-by: Borislav Petkov 
Cc: tglx@linutronix.de
Cc: mingo@redhat.com
Cc: hpa@zytor.com
Cc: tony.luck@intel.com
Cc: thomas.lendacky@amd.com
Cc: linux-edac@vger.kernel.org
Link: https://lkml.kernel.org/r/87d8a4f16bdea0bfe0c0cf2e4a8d2c2a99b1055c.1537533369.git.puwen@hygon.cn

x86/mce-inject: Reset injection struct after injection

2018-09-21T12:28:37+00:00

Clear the MCE struct which is used for collecting the injection details
after injection.

Also, populate it with more details from the machine.

Signed-off-by: Borislav Petkov 
Link: https://lkml.kernel.org/r/20180905081954.10391-1-bp@alien8.de