linux-toradex.git/arch/x86/kernel/cpu/perf_event_p4.c, branch v3.10.76

perf/x86/intel/P4: Robistify P4 PMU types

2013-04-26T07:31:41+00:00

Linus found, while extending integer type extension checks in the
sparse static code checker, various fragile patterns of mixed
signed/unsigned  64-bit/32-bit integer use in perf_events_p4.c.

The relevant hardware register ABI is 64 bit wide on 32-bit
kernels as  well, so clean it all up a bit, remove unnecessary
casts, and make sure we  use 64-bit unsigned integers in these
places.

[ Unfortunately this patch was not tested on real P4 hardware,
  those are pretty rare already. If this patch causes any
  problems on P4 hardware then please holler ... ]

Reported-by: Linus Torvalds 
Signed-off-by: Ingo Molnar 
Cc: David Miller 
Cc: Theodore Ts'o 
Cc: Oleg Nesterov 
Cc: Frederic Weisbecker 
Cc: Cyrill Gorcunov 
Cc: Peter Zijlstra 
Link: http://lkml.kernel.org/r/20130424072630.GB1780@gmail.com
Signed-off-by: Ingo Molnar

perf/x86: Rename Intel specific macros

2012-07-05T19:19:39+00:00

There are macros that are Intel specific and not x86 generic. Rename
them into INTEL_*.

This patch removes X86_PMC_IDX_GENERIC and does:

 $ sed -i -e 's/X86_PMC_MAX_/INTEL_PMC_MAX_/g'           \
         arch/x86/include/asm/kvm_host.h                 \
         arch/x86/include/asm/perf_event.h               \
         arch/x86/kernel/cpu/perf_event.c                \
         arch/x86/kernel/cpu/perf_event_p4.c             \
         arch/x86/kvm/pmu.c
 $ sed -i -e 's/X86_PMC_IDX_FIXED/INTEL_PMC_IDX_FIXED/g' \
         arch/x86/include/asm/perf_event.h               \
         arch/x86/kernel/cpu/perf_event.c                \
         arch/x86/kernel/cpu/perf_event_intel.c          \
         arch/x86/kernel/cpu/perf_event_intel_ds.c       \
         arch/x86/kvm/pmu.c
 $ sed -i -e 's/X86_PMC_MSK_/INTEL_PMC_MSK_/g'           \
         arch/x86/include/asm/perf_event.h               \
         arch/x86/kernel/cpu/perf_event.c

Signed-off-by: Robert Richter 
Signed-off-by: Peter Zijlstra 
Link: http://lkml.kernel.org/r/1340217996-2254-2-git-send-email-robert.richter@amd.com
Signed-off-by: Ingo Molnar

x86, cpu: Rename checking_wrmsrl() to wrmsrl_safe()

2012-06-07T20:32:04+00:00

Rename checking_wrmsrl() to wrmsrl_safe(), to match the naming
convention used by all the other MSR access functions/macros.

Signed-off-by: H. Peter Anvin

perf: Pass last sampling period to perf_sample_data_init()

2012-05-09T13:23:12+00:00

We always need to pass the last sample period to
perf_sample_data_init(), otherwise the event distribution will be
wrong. Thus, modifiyng the function interface with the required period
as argument. So basically a pattern like this:

        perf_sample_data_init(&data, ~0ULL);
        data.period = event->hw.last_period;

will now be like that:

        perf_sample_data_init(&data, ~0ULL, event->hw.last_period);

Avoids unininitialized data.period and simplifies code.

Signed-off-by: Robert Richter 
Signed-off-by: Peter Zijlstra 
Link: http://lkml.kernel.org/r/1333390758-10893-3-git-send-email-robert.richter@amd.com
Signed-off-by: Ingo Molnar

perf/x86/p4: Add format attributes

2012-04-03T06:33:38+00:00

Steven reported his P4 not booting properly, the missing format
attributes cause a NULL ptr deref. Cure this by adding the
missing format specification.

I took the format description out of the comment near
p4_config_pack*() and hope that comment is still relatively
accurate.

Reported-by: Steven Rostedt 
Reported-by: Bruno Prémont 
Tested-by: Steven Rostedt 
Signed-off-by: Peter Zijlstra 
Cc: Jiri Olsa 
Cc: Cyrill Gorcunov 
Cc: Lin Ming 
Cc: Stephane Eranian 
Link: http://lkml.kernel.org/r/1332859842.16159.227.camel@twins
Signed-off-by: Ingo Molnar

perf: Don't use -ENOSPC for out of PMU resources

2011-11-14T12:01:24+00:00

People (Linus) objected to using -ENOSPC to signal not having enough
resources on the PMU to satisfy the request. Use -EINVAL.

Requested-by: Linus Torvalds 
Cc: Stephane Eranian 
Cc: Will Deacon 
Cc: Deng-Cheng Zhu 
Cc: David Daney 
Cc: Ralf Baechle 
Signed-off-by: Peter Zijlstra 
Link: http://lkml.kernel.org/n/tip-xv8geaz2zpbjhlx0svmpp28n@git.kernel.org
[ merged to newer kernel, fixed up MIPS impact ]
Signed-off-by: Ingo Molnar

x86, perf: Clean up perf_event cpu code

2011-09-26T10:58:00+00:00

The CPU support for perf events on x86 was implemented via included C files
with #ifdefs.  Clean this up by creating a new header file and compiling
the vendor-specific files as needed.

Signed-off-by: Kevin Winchester 
Signed-off-by: Peter Zijlstra 
Link: http://lkml.kernel.org/r/1314747665-2090-1-git-send-email-kjwinchester@gmail.com
Signed-off-by: Ingo Molnar

x86, perf: P4 PMU - Fix typos in comments and style cleanup

2011-07-21T18:41:54+00:00

This patch:

 - fixes typos in comments and clarifies the text
 - renames obscure p4_event_alias::original and ::alter members to
   ::original and ::alternative as appropriate
 - drops parenthesis from the return of p4_get_alias_event()

No functional changes.

Reported-by: Ingo Molnar 
Signed-off-by: Cyrill Gorcunov 
Link: http://lkml.kernel.org/r/20110721160625.GX7492@sun
Signed-off-by: Ingo Molnar

perf, x86: P4 PMU - Introduce event alias feature

2011-07-14T21:25:04+00:00

Instead of hw_nmi_watchdog_set_attr() weak function
and appropriate x86_pmu::hw_watchdog_set_attr() call
we introduce even alias mechanism which allow us
to drop this routines completely and isolate quirks
of Netburst architecture inside P4 PMU code only.

The main idea remains the same though -- to allow
nmi-watchdog and perf top run simultaneously.

Note the aliasing mechanism applies to generic
PERF_COUNT_HW_CPU_CYCLES event only because arbitrary
event (say passed as RAW initially) might have some
additional bits set inside ESCR register changing
the behaviour of event and we can't guarantee anymore
that alias event will give the same result.

P.S. Thanks a huge to Don and Steven for for testing
     and early review.

Acked-by: Don Zickus 
Tested-by: Steven Rostedt 
Signed-off-by: Cyrill Gorcunov 
CC: Ingo Molnar 
CC: Peter Zijlstra 
CC: Stephane Eranian 
CC: Lin Ming 
CC: Arnaldo Carvalho de Melo 
CC: Frederic Weisbecker 
Link: http://lkml.kernel.org/r/20110708201712.GS23657@sun
Signed-off-by: Steven Rostedt

perf, arch: Add generic NODE cache events

2011-07-01T09:06:38+00:00

Add a NODE level to the generic cache events which is used to measure
local vs remote memory accesses. Like all other cache events, an
ACCESS is HIT+MISS, if there is no way to distinguish between reads
and writes do reads only etc..

The below needs filling out for !x86 (which I filled out with
unsupported events).

I'm fairly sure ARM can leave it like that since it doesn't strike me as
an architecture that even has NUMA support. SH might have something since
it does appear to have some NUMA bits.

Sparc64, PowerPC and MIPS certainly want a good look there since they
clearly are NUMA capable.

Signed-off-by: Peter Zijlstra 
Cc: David Miller 
Cc: Anton Blanchard 
Cc: David Daney 
Cc: Deng-Cheng Zhu 
Cc: Paul Mundt 
Cc: Will Deacon 
Cc: Robert Richter 
Cc: Stephane Eranian 
Link: http://lkml.kernel.org/r/1303508226.4865.8.camel@laptop
Signed-off-by: Ingo Molnar