linux-toradex.git/arch/x86/kernel/cpu/perf_event_p6.c, branch v4.4.87

perf/x86/intel/p6: Add userspace RDPMC quirk for PPro

2014-02-09T12:08:24+00:00

PPro machines can die hard when PCE gets enabled due to a CPU erratum.
The safe way it so disable it by default and keep it disabled.

See erratum 26 in:

  http://download.intel.com/design/archives/processors/pro/docs/24268935.pdf

Reported-and-Tested-by: Mark Davies 
Cc: Alan Cox 
Cc: Stephane Eranian 
Cc: Vince Weaver 
Signed-off-by: Peter Zijlstra 
Link: http://lkml.kernel.org/r/20140206170815.GW2936@laptop.programming.kicks-ass.net
Signed-off-by: Ingo Molnar

x86: Constify a few items

2013-03-11T14:11:03+00:00

This in particular re-does the compiler warning fix 9faec5b
("perf/x86: Fix P6 driver section warning"), tightening the
section attributes rather than relaxing them.

Signed-off-by: Jan Beulich 
Cc: Shaun Ruffell 
Cc: yangyongqiang 
Cc: Cyrill Gorcunov 
Cc: Vince Weaver 
Link: http://lkml.kernel.org/r/513DB84502000078000C4880@nat28.tlf.novell.com
Signed-off-by: Ingo Molnar

perf/x86: Fix P6 driver section warning

2013-01-24T15:04:56+00:00

Fix a compile warning - 'a section type conflict' by removing
__initconst.

Signed-off-by: yangyongqiang 
Cc: Cyrill Gorcunov 
Cc: Vince Weaver 
Signed-off-by: Andrew Morton 
Signed-off-by: Ingo Molnar

Merge branch 'linus' into perf/core

2012-12-08T14:25:06+00:00

Conflicts:
	tools/perf/Makefile
	tools/perf/builtin-test.c
	tools/perf/perf.h
	tools/perf/tests/parse-events.c
	tools/perf/util/evsel.h

Signed-off-by: Ingo Molnar

perf/x86: Add hardware events translations for Intel P6 cpus

2012-10-24T08:41:25+00:00

Add support for Intel P6 processors to display 'events' sysfs
directory (/sys/devices/cpu/events/) with hw event translations:

  # ls /sys/devices/cpu/events/
  branch-instructions
  branch-misses
  bus-cycles
  cache-misses
  cache-references
  cpu-cycles
  instructions
  ref-cycles
  stalled-cycles-backend
  stalled-cycles-frontend

Suggested-by: Peter Zijlstra 
Signed-off-by: Jiri Olsa 
Cc: Vince Weaver 
Cc: Arnaldo Carvalho de Melo 
Cc: Paul Mackerras 
Cc: Corey Ashford 
Cc: Frederic Weisbecker 
Cc: Stephane Eranian 
Signed-off-by: Peter Zijlstra 
Link: http://lkml.kernel.org/r/1349873598-12583-6-git-send-email-jolsa@redhat.com
Signed-off-by: Ingo Molnar

perf/x86: Remove P6 cpuc->enabled check

2012-10-24T08:32:00+00:00

Between 2.6.33 and 2.6.34 the PMU code was made modular.

The x86_pmu_enable() call was extended to disable cpuc->enabled
and iterate the counters, enabling one at a time, before calling
enable_all() at the end, followed by re-enabling cpuc->enabled.

Since cpuc->enabled was set to 0, that change effectively caused
the "val |= ARCH_PERFMON_EVENTSEL_ENABLE;" code in p6_pmu_enable_event()
and p6_pmu_disable_event() to be dead code that was never called.

This change removes this code (which was confusing) and adds some
extra commentary to make it more clear what is going on.

Signed-off-by: Vince Weaver 
Signed-off-by: Peter Zijlstra 
Link: http://lkml.kernel.org/r/alpine.DEB.2.02.1210191732000.14552@vincent-weaver-1.um.maine.edu
Signed-off-by: Ingo Molnar

perf/x86: Update/fix generic events on P6 PMU

2012-10-24T08:31:58+00:00

This patch updates the generic events on p6, including some new
extended cache events.

Values for these events were taken from the equivelant PAPI
predefined events.

Tested on a Pentium II.

Signed-off-by: Vince Weaver 
Signed-off-by: Peter Zijlstra 
Link: http://lkml.kernel.org/r/alpine.DEB.2.02.1210191730080.14552@vincent-weaver-1.um.maine.edu
Signed-off-by: Ingo Molnar

perf/x86: Fix P6 FP_ASSIST event constraint

2012-10-24T08:31:57+00:00

According to Intel SDM Volume 3B, FP_ASSIST is limited to Counter 1 only,
not Counter 0.

Tested on a Pentium II.

Signed-off-by: Vince Weaver 
Signed-off-by: Peter Zijlstra 
Link: http://lkml.kernel.org/r/alpine.DEB.2.02.1210191728570.14552@vincent-weaver-1.um.maine.edu
Signed-off-by: Ingo Molnar

x86, cpu: Rename checking_wrmsrl() to wrmsrl_safe()

2012-06-07T20:32:04+00:00

Rename checking_wrmsrl() to wrmsrl_safe(), to match the naming
convention used by all the other MSR access functions/macros.

Signed-off-by: H. Peter Anvin

perf: Adding sysfs group format attribute for pmu device

2012-03-16T17:06:06+00:00

Adding sysfs group 'format' attribute for pmu device that
contains a syntax description on how to construct raw events.

The event configuration is described in following
struct pefr_event_attr attributes:

  config
  config1
  config2

Each sysfs attribute within the format attribute group,
describes mapping of name and bitfield definition within
one of above attributes.

eg:
  "/sys/.../format/event" contains "config:0-7"
  "/sys/.../format/umask" contains "config:8-15"
  "/sys/.../format/usr"   contains "config:16"

the attribute value syntax is:

  line:      config ':' bits
  config:    'config' | 'config1' | 'config2"
  bits:      bits ',' bit_term | bit_term
  bit_term:  VALUE '-' VALUE | VALUE

Adding format attribute definitions for x86 cpu pmus.

Acked-by: Peter Zijlstra 
Signed-off-by: Peter Zijlstra 
Signed-off-by: Jiri Olsa 
Link: http://lkml.kernel.org/n/tip-vhdk5y2hyype9j63prymty36@git.kernel.org
Signed-off-by: Arnaldo Carvalho de Melo