linux-toradex.git/arch/x86/kernel/cpu, branch v4.1.9

x86/mce: Reenable CMCI banks when swiching back to interrupt mode

2015-09-21T17:05:43+00:00

commit 1b48465500611a2dc5e75800c61ac352e22d41c3 upstream.

Zhang Liguang reported the following issue:

1) System detects a CMCI storm on the current CPU.

2) Kernel disables the CMCI interrupt on banks owned by the
   current CPU and switches to poll mode

3) After the CMCI storm subsides, kernel switches back to
   interrupt mode

4) We expect the system to reenable the CMCI interrupt on banks
   owned by the current CPU

   mce_intel_adjust_timer
   |-> cmci_reenable
       |-> cmci_discover     # owned banks are ignored here

  static void cmci_discover(int banks)
	...
	for (i = 0; i < banks; i++) {
		...
		if (test_bit(i, owned))	# ownd banks is ignore here
			continue;

So convert cmci_storm_disable_banks() to
cmci_toggle_interrupt_mode() which controls whether to enable or
disable CMCI interrupts with its argument.

NB: We cannot clear the owned bit because the banks won't be
polled, otherwise. See:

  27f6c573e0f7 ("x86, CMCI: Add proper detection of end of CMCI storms")

for more info.

Reported-by: Zhang Liguang 
Signed-off-by: Xie XiuQi 
Signed-off-by: Borislav Petkov 
Cc: H. Peter Anvin 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Cc: Tony Luck 
Cc: huawei.libin@huawei.com
Cc: linux-edac 
Cc: rui.xiang@huawei.com
Link: http://lkml.kernel.org/r/1439396985-12812-10-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar 
Signed-off-by: Greg Kroah-Hartman

x86/ldt: Make modify_ldt synchronous

2015-09-21T17:05:25+00:00

commit 37868fe113ff2ba814b3b4eb12df214df555f8dc upstream.

modify_ldt() has questionable locking and does not synchronize
threads.  Improve it: redesign the locking and synchronize all
threads' LDTs using an IPI on all modifications.

This will dramatically slow down modify_ldt in multithreaded
programs, but there shouldn't be any multithreaded programs that
care about modify_ldt's performance in the first place.

This fixes some fallout from the CVE-2015-5157 fixes.

Signed-off-by: Andy Lutomirski 
Reviewed-by: Borislav Petkov 
Cc: Andrew Cooper 
Cc: Andy Lutomirski 
Cc: Boris Ostrovsky 
Cc: Borislav Petkov 
Cc: Brian Gerst 
Cc: Denys Vlasenko 
Cc: H. Peter Anvin 
Cc: Jan Beulich 
Cc: Konrad Rzeszutek Wilk 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Sasha Levin 
Cc: Steven Rostedt 
Cc: Thomas Gleixner 
Cc: security@kernel.org 
Cc: xen-devel 
Link: http://lkml.kernel.org/r/4c6978476782160600471bd865b318db34c7b628.1438291540.git.luto@kernel.org
Signed-off-by: Ingo Molnar 
Signed-off-by: Greg Kroah-Hartman

perf/x86/intel/cqm: Return cached counter value from IRQ context

2015-08-10T19:21:58+00:00

commit 2c534c0da0a68418693e10ce1c4146e085f39518 upstream.

Peter reported the following potential crash which I was able to
reproduce with his test program,

[  148.765788] ------------[ cut here ]------------
[  148.765796] WARNING: CPU: 34 PID: 2840 at kernel/smp.c:417 smp_call_function_many+0xb6/0x260()
[  148.765797] Modules linked in:
[  148.765800] CPU: 34 PID: 2840 Comm: perf Not tainted 4.2.0-rc1+ #4
[  148.765803]  ffffffff81cdc398 ffff88085f105950 ffffffff818bdfd5 0000000000000007
[  148.765805]  0000000000000000 ffff88085f105990 ffffffff810e413a 0000000000000000
[  148.765807]  ffffffff82301080 0000000000000022 ffffffff8107f640 ffffffff8107f640
[  148.765809] Call Trace:
[  148.765810]    [] dump_stack+0x45/0x57
[  148.765818]  [] warn_slowpath_common+0x8a/0xc0
[  148.765822]  [] ? intel_cqm_stable+0x60/0x60
[  148.765824]  [] ? intel_cqm_stable+0x60/0x60
[  148.765825]  [] warn_slowpath_null+0x1a/0x20
[  148.765827]  [] smp_call_function_many+0xb6/0x260
[  148.765829]  [] ? intel_cqm_stable+0x60/0x60
[  148.765831]  [] on_each_cpu_mask+0x28/0x60
[  148.765832]  [] intel_cqm_event_count+0x7f/0xe0
[  148.765836]  [] perf_output_read+0x2a5/0x400
[  148.765839]  [] perf_output_sample+0x31a/0x590
[  148.765840]  [] ? perf_prepare_sample+0x26d/0x380
[  148.765841]  [] perf_event_output+0x47/0x60
[  148.765843]  [] __perf_event_overflow+0x215/0x240
[  148.765844]  [] perf_event_overflow+0x14/0x20
[  148.765847]  [] intel_pmu_handle_irq+0x1d4/0x440
[  148.765849]  [] ? __perf_event_task_sched_in+0x36/0xa0
[  148.765853]  [] ? vunmap_page_range+0x19d/0x2f0
[  148.765854]  [] ? unmap_kernel_range_noflush+0x11/0x20
[  148.765859]  [] ? ghes_copy_tofrom_phys+0x11e/0x2a0
[  148.765863]  [] ? native_apic_msr_write+0x2b/0x30
[  148.765865]  [] ? x2apic_send_IPI_self+0x1d/0x20
[  148.765869]  [] ? arch_irq_work_raise+0x35/0x40
[  148.765872]  [] ? irq_work_queue+0x66/0x80
[  148.765875]  [] perf_event_nmi_handler+0x26/0x40
[  148.765877]  [] nmi_handle+0x79/0x100
[  148.765879]  [] default_do_nmi+0x42/0x100
[  148.765880]  [] do_nmi+0x83/0xb0
[  148.765884]  [] end_repeat_nmi+0x1e/0x2e
[  148.765886]  [] ? __perf_event_task_sched_in+0x36/0xa0
[  148.765888]  [] ? __perf_event_task_sched_in+0x36/0xa0
[  148.765890]  [] ? __perf_event_task_sched_in+0x36/0xa0
[  148.765891]  <>  [] finish_task_switch+0x156/0x210
[  148.765898]  [] __schedule+0x341/0x920
[  148.765899]  [] schedule+0x37/0x80
[  148.765903]  [] ? do_page_fault+0x2f/0x80
[  148.765905]  [] schedule_user+0x1a/0x50
[  148.765907]  [] retint_careful+0x14/0x32
[  148.765908] ---[ end trace e33ff2be78e14901 ]---

The CQM task events are not safe to be called from within interrupt
context because they require performing an IPI to read the counter value
on all sockets. And performing IPIs from within IRQ context is a
"no-no".

Make do with the last read counter value currently event in
event->count when we're invoked in this context.

Reported-by: Peter Zijlstra 
Signed-off-by: Matt Fleming 
Cc: Thomas Gleixner 
Cc: Vikas Shivappa 
Cc: Kanaka Juvva 
Cc: Will Auld 
Link: http://lkml.kernel.org/r/1437490509-15373-1-git-send-email-matt@codeblueprint.co.uk
Signed-off-by: Thomas Gleixner 
Signed-off-by: Greg Kroah-Hartman

perf/x86: Honor the architectural performance monitoring version

2015-06-29T19:35:28+00:00

commit 2c33645d366d13b969d936b68b9f4875b1fdddea upstream.

Architectural performance monitoring, version 1, doesn't support fixed counters.

Currently, even if a hypervisor advertises support for architectural
performance monitoring version 1, perf may still try to use the fixed
counters, as the constraints are set up based on the CPU model.

This patch ensures that perf honors the architectural performance monitoring
version returned by CPUID, and it only uses the fixed counters for version 2
and above.

(Some of the ideas in this patch came from Peter Zijlstra.)

Signed-off-by: Imre Palik 
Signed-off-by: Peter Zijlstra (Intel) 
Cc: Andrew Morton 
Cc: Andy Lutomirski 
Cc: Anthony Liguori 
Cc: Arnaldo Carvalho de Melo 
Cc: Borislav Petkov 
Cc: Brian Gerst 
Cc: Denys Vlasenko 
Cc: H. Peter Anvin 
Cc: Linus Torvalds 
Cc: Oleg Nesterov 
Cc: Paul Mackerras 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Link: http://lkml.kernel.org/r/1433767609-1039-1-git-send-email-imrep.amz@gmail.com
Signed-off-by: Ingo Molnar 
Signed-off-by: Greg Kroah-Hartman

perf/x86/intel/bts: Fix DS area sharing with x86_pmu events

2015-06-29T19:35:28+00:00

commit 6b099d9b040b0f3d0aec05b560d7caf879af5077 upstream.

Currently, the intel_bts driver relies on the DS area allocated by the x86_pmu
code in its event_init() path, which is a bug: creating a BTS event while
no x86_pmu events are present results in a NULL pointer dereference.

The same DS area is also used by PEBS sampling, which makes it quite a bit
trickier to have a separate one for intel_bts' purposes.

This patch makes intel_bts driver use the same DS allocation and reference
counting code as x86_pmu to make sure it is always present when either
intel_bts or x86_pmu need it.

Signed-off-by: Alexander Shishkin 
Signed-off-by: Peter Zijlstra (Intel) 
Cc: Andrew Morton 
Cc: Andy Lutomirski 
Cc: Borislav Petkov 
Cc: Brian Gerst 
Cc: Denys Vlasenko 
Cc: H. Peter Anvin 
Cc: Linus Torvalds 
Cc: Oleg Nesterov 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Cc: acme@infradead.org
Cc: adrian.hunter@intel.com
Link: http://lkml.kernel.org/r/1434024837-9916-2-git-send-email-alexander.shishkin@linux.intel.com
Signed-off-by: Ingo Molnar 
Signed-off-by: Greg Kroah-Hartman

perf/x86: Add more Broadwell model numbers

2015-06-29T19:35:28+00:00

commit 4b36f1a4139c9284df74c0f5d7655603d67807df upstream.

This patch adds additional model numbers for Broadwell to perf.
Support for Broadwell with Iris Pro (Intel Core i7-57xxC)
and support for Broadwell Server Xeon.

Signed-off-by: Andi Kleen 
Signed-off-by: Peter Zijlstra (Intel) 
Cc: Andrew Morton 
Cc: Andy Lutomirski 
Cc: Borislav Petkov 
Cc: Brian Gerst 
Cc: Denys Vlasenko 
Cc: H. Peter Anvin 
Cc: Linus Torvalds 
Cc: Oleg Nesterov 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Link: http://lkml.kernel.org/r/1434055942-28253-1-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar 
Signed-off-by: Greg Kroah-Hartman

Revert "perf/x86/intel/uncore: Move uncore_box_init() out of driver initialization"

2015-06-09T09:44:37+00:00

This reverts commit c05199e5a57a579fea1e8fa65e2b511ceb524ffc.

Vince Weaver reported the following crash while perf fuzzing:

[   79.473121] kernel BUG at mm/vmalloc.c:1335!
[   79.694391] Call Trace:
[   79.696997]  
[   79.699090]  [] get_vm_area_caller+0x40/0x50
[   79.705505]  [] ? snb_uncore_imc_init_box+0x6d/0x90
[   79.712414]  [] __ioremap_caller+0x195/0x350
[   79.718610]  [] ? snb_uncore_imc_init_box+0x6d/0x90
[   79.725462]  [] ? debug_object_activate+0x14b/0x1e0
[   79.732346]  [] ioremap_nocache+0x17/0x20
[   79.738283]  [] snb_uncore_imc_init_box+0x6d/0x90
[   79.744945]  [] snb_uncore_imc_event_start+0xb7/0x110
[   79.752020]  [] snb_uncore_imc_event_add+0x47/0x60
[   79.758832]  [] event_sched_in.isra.85+0xfb/0x330
[   79.765519]  [] group_sched_in+0x6f/0x1e0
[   79.771481]  [] ? native_sched_clock+0x2a/0x90
[   79.777858]  [] __perf_event_enable+0x25c/0x2a0
[   79.784418]  [] ? tick_nohz_irq_exit+0x29/0x30
[   79.790820]  [] ? cpu_clock_event_start+0x40/0x40
[   79.797546]  [] remote_function+0x50/0x60
[   79.803535]  [] flush_smp_call_function_queue+0x81/0x180
[   79.810840]  [] generic_smp_call_function_single_interrupt+0x13/0x60
[   79.819328]  [] smp_trace_call_function_single_interrupt+0x38/0xc0
[   79.827614]  [] trace_call_function_single_interrupt+0x6e/0x80
[   79.835465]  
[   79.837543]  [] ? cpuidle_enter_state+0x65/0x160
[   79.844377]  [] ? cpuidle_enter_state+0x51/0x160
[   79.851015]  [] cpuidle_enter+0x17/0x20
[   79.856791]  [] cpu_startup_entry+0x399/0x440
[   79.863165]  [] rest_init+0xbb/0xd0

The offending commit is clearly confused as it moves heavy initialization
work into IPI context.

Revert it.

Reported-by: Vince Weaver 
Acked-by: Peter Zijlstra (Intel) 
Cc: Kan Liang 
Cc: Arnaldo Carvalho de Melo 
Cc: Stephane Eranian 
Cc: Yan, Zheng 
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Ingo Molnar

perf/x86/intel/uncore: Fix CBOX bit wide and UBOX reg on Haswell-EP

2015-06-07T13:46:50+00:00

CBOX counters are increased to 48b on HSX.

Correct the MSR address for HSWEP_U_MSR_PMON_CTR0 and
HSWEP_U_MSR_PMON_CTL0.

See specification in:
http://www.intel.com/content/www/us/en/processors/xeon/
xeon-e5-v3-uncore-performance-monitoring.html

Signed-off-by: Kan Liang 
Signed-off-by: Peter Zijlstra (Intel) 
Cc: Andrew Morton 
Cc: H. Peter Anvin 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Link: http://lkml.kernel.org/r/1432645835-7918-1-git-send-email-kan.liang@intel.com
Signed-off-by: Ingo Molnar

Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

2015-06-05T17:00:53+00:00

Pull perf fixes from Ingo Molnar:
 "The biggest chunk of the changes are two regression fixes: a HT
  workaround fix and an event-group scheduling fix.  It's been verified
  with 5 days of fuzzer testing.

  Other fixes:

   - eBPF fix
   - a BIOS breakage detection fix
   - PMU driver fixes"

* 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  perf/x86/intel/pt: Fix a refactoring bug
  perf/x86: Tweak broken BIOS rules during check_hw_exists()
  perf/x86/intel/pt: Untangle pt_buffer_reset_markers()
  perf: Disallow sparse AUX allocations for non-SG PMUs in overwrite mode
  perf/x86: Improve HT workaround GP counter constraint
  perf/x86: Fix event/group validation
  perf: Fix race in BPF program unregister

perf/x86/intel/pt: Fix a refactoring bug

2015-06-04T14:07:51+00:00

Commit 066450be41 ("perf/x86/intel/pt: Clean up the control flow
in pt_pmu_hw_init()") changed attribute initialization so that
only the first attribute gets initialized using
sysfs_attr_init(), which upsets lockdep.

This patch fixes the glitch so that all allocated attributes are
properly initialized thus fixing the lockdep warning reported by
Tvrtko and Imre.

Reported-by: Tvrtko Ursulin 
Reported-by: Imre Deak 
Signed-off-by: Alexander Shishkin 
Cc: 
Cc: Andrew Morton 
Cc: H. Peter Anvin 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Signed-off-by: Ingo Molnar