linux-toradex.git/arch/x86_64/kernel/apic.c, branch v2.6.16.42 Linux kernel for Apalis and Colibri modules Revert "[PATCH] x86_64: Only do the clustered systems have unsynchronized TSC assumption on IBM systems" 2006-02-28T04:41:56+00:00 Linus Torvalds torvalds@g5.osdl.org 2006-02-28T04:41:56+00:00 637029c6cb5efcbaa3d5831af4c1972bdd629779 This reverts commit 13a229abc25640813f1480c0478dfc6bdbc1c19e. Quoth Andi: "After some consideration and feedback from various people it turns out this wasn't that good an idea. It has some problems and needs more work. Since it was only an optimization anyways it's best to just back it out again for now." Signed-off-by: Linus Torvalds <torvalds@osdl.org> 
This reverts commit 13a229abc25640813f1480c0478dfc6bdbc1c19e.

Quoth Andi:
  "After some consideration and feedback from various people it turns
   out this wasn't that good an idea.  It has some problems and needs
   more work.  Since it was only an optimization anyways it's best to
   just back it out again for now."

Signed-off-by: Linus Torvalds <torvalds@osdl.org>
[PATCH] x86_64: Only do the clustered systems have unsynchronized TSC assumption on IBM systems 2006-02-26T17:53:30+00:00 Andi Kleen ak@suse.de 2006-02-26T03:18:31+00:00 13a229abc25640813f1480c0478dfc6bdbc1c19e Big Unisys systems have multiple clusters too, but they have an synchronized TSC. I'm using the SMBIOS to check for vendor == IBM. Cc: Chris McDermott <lcm@us.ibm.com> Cc: "Protasevich, Natalie" <Natalie.Protasevich@unisys.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org> 
Big Unisys systems have multiple clusters too, but they have an
synchronized TSC.

I'm using the SMBIOS to check for vendor == IBM.

Cc: Chris McDermott <lcm@us.ibm.com>
Cc: "Protasevich, Natalie" <Natalie.Protasevich@unisys.com>

Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
[PATCH] x86_64: Disable tsc when apicpmtimer is active 2006-02-17T16:00:40+00:00 Andi Kleen ak@suse.de 2006-02-16T22:42:07+00:00 7fd67843b96f90f59c9a244a1bc25137978a3ff9 Otherwise it has no effect anyways. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org> 
Otherwise it has no effect anyways.

Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
[PATCH] x86-64: Fix HPET timer on x460 2006-02-12T05:41:11+00:00 Chris McDermott lcm@us.ibm.com 2006-02-12T01:55:50+00:00 33042a9ff4d126ba944b9dc3076665a2029e0a34 [description from AK] The IBM Summit 3 chipset doesn't implement the HPET timer replacement option. Since the current Linux code relies on it use a mixed mode with both PIT for the interrupt and HPET counters for the time keeping. That was already implemented, but didn't work properly because it was still using the last interrupt offset in HPET. This resulted in x460 not booting. Fix this up by using the free running HPET counter. Shouldn't affect any other machine because they either use full HPET mode or no HPET at all. TBD needs a similar 32bit fix. Signed-off-by: Andi Kleen <ak@suse.de> Cc: Pallipadi, Venkatesh" <venkatesh.pallipadi@intel.com> Cc: Bob Picco <bob.picco@hp.com> Cc: Bjorn Helgaas <bjorn.helgaas@hp.com> Cc: john stultz <johnstul@us.ibm.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org> 
[description from AK]

The IBM Summit 3 chipset doesn't implement the HPET timer replacement
option.  Since the current Linux code relies on it use a mixed mode with
both PIT for the interrupt and HPET counters for the time keeping.  That
was already implemented, but didn't work properly because it was still
using the last interrupt offset in HPET.  This resulted in x460 not
booting.  Fix this up by using the free running HPET counter.

Shouldn't affect any other machine because they either use full HPET mode
or no HPET at all.

TBD needs a similar 32bit fix.

Signed-off-by: Andi Kleen <ak@suse.de>
Cc: Pallipadi, Venkatesh" <venkatesh.pallipadi@intel.com>
Cc: Bob Picco <bob.picco@hp.com>
Cc: Bjorn Helgaas <bjorn.helgaas@hp.com>
Cc: john stultz <johnstul@us.ibm.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
[PATCH] i386/x86-64: Don't ack the APIC for bad interrupts when the APIC is not enabled 2006-02-05T00:43:15+00:00 Andi Kleen ak@suse.de 2006-02-03T20:51:53+00:00 3777a95903953c55f2309a89679b73c19ae5535b It's bad juju to touch the APIC when it hasn't been enabled. I also moved ack_bad_irq for x86-64 out of line following i386. Signed-off-by: Andi Kleen <ak@suse.de> Acked-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Linus Torvalds <torvalds@osdl.org> 
It's bad juju to touch the APIC when it hasn't been enabled.
I also moved ack_bad_irq for x86-64 out of line following i386.

Signed-off-by: Andi Kleen <ak@suse.de>
Acked-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
[PATCH] x86_64: Calibrate APIC timer using PM timer 2006-02-05T00:43:15+00:00 Andi Kleen ak@suse.de 2006-02-03T20:51:41+00:00 0c3749c41f5eee0da36bbf92b2793338b4d8574f On some broken motherboards (at least one NForce3 based AMD64 laptop) the PIT timer runs at a incorrect frequency. This patch adds a new option "apicpmtimer" that allows to use the APIC timer and calibrate it using the PMTimer. It requires the earlier patch that allows to run the main timer from the APIC. Specifying apicpmtimer implies apicmaintimer. The option defaults to off for now. I tested it on a few systems and the resulting APIC timer frequencies were usually a bit off, but always <1%, which should be tolerable. TBD figure out heuristic to enable this automatically on the affected systems TBD perhaps do it on all NForce3s or using DMI? Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org> 
On some broken motherboards (at least one NForce3 based AMD64 laptop)
the PIT timer runs at a incorrect frequency.  This patch adds a new
option "apicpmtimer" that allows to use the APIC timer and calibrate it
using the PMTimer.  It requires the earlier patch that allows to run the
main timer from the APIC.

Specifying apicpmtimer implies apicmaintimer.

The option defaults to off for now.

I tested it on a few systems and the resulting APIC timer frequencies
were usually a bit off, but always <1%, which should be tolerable.

TBD figure out heuristic to enable this automatically on the affected
systems TBD perhaps do it on all NForce3s or using DMI?

Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
[PATCH] x86_64: mark two routines as __cpuinit 2006-02-05T00:43:14+00:00 Shaohua Li shaohua.li@intel.com 2006-02-03T20:51:20+00:00 396bd50fed9c91f7aa1ac66f4b2880ca58c332ff SIgned-off-by: Shaohua Li<shaohua.li@intel.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org> 
SIgned-off-by: Shaohua Li<shaohua.li@intel.com>
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
[PATCH] x86_64: Allow to run main time keeping from the local APIC interrupt 2006-02-05T00:43:13+00:00 Andi Kleen ak@suse.de 2006-02-03T20:50:50+00:00 73dea47faeb96d54a984b9d7f4de564816966354 Another piece from the no-idle-tick patch. This can be enabled with the "apicmaintimer" option. This is mainly useful when the PIT/HPET interrupt is unreliable. Note there are some systems that are known to stop the APIC timer in C3. For those it will never work, but this case should be automatically detected. It also only works with PM timer right now. When HPET is used the way the main timer handler computes the delay doesn't work. It should be a bit more efficient because there is one less regular interrupt to process on the boot processor. Requires earlier bugfix from Venkatesh Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org> 
Another piece from the no-idle-tick patch.

This can be enabled with the "apicmaintimer" option.

This is mainly useful when the PIT/HPET interrupt is unreliable.
Note there are some systems that are known to stop the APIC
timer in C3. For those it will never work, but this case
should be automatically detected.

It also only works with PM timer right now. When HPET is used
the way the main timer handler computes the delay doesn't work.

It should be a bit more efficient because there is one less
regular interrupt to process on the boot processor.

Requires earlier bugfix from Venkatesh

Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
[PATCH] x86_64: lapic resume uses correct base address 2006-01-16T19:27:59+00:00 Shaohua Li shaohua.li@intel.com 2006-01-16T00:56:45+00:00 5b74357328eb325c12ea76f043524e7924a021e4 uses correct lapic base address. The set_fixmap appears useless. Signed-off-by: Shaohua Li<shaohua.li@intel.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org> 
uses correct lapic base address. The set_fixmap appears useless.

Signed-off-by: Shaohua Li<shaohua.li@intel.com>
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
[PATCH] x86_64: Some housekeeping in local APIC code 2006-01-12T03:05:03+00:00 Andi Kleen ak@suse.de 2006-01-11T21:46:51+00:00 11a8e778c46ee76fc46b0a7fa9d455b5a8e3e19f Remove support for obsolete hardware and cleanup. - Remove checks for non integrated APICs - Replace apic_write_around with apic_write. - Remove apic_read_around - Remove APIC version reads used by old workarounds - Remove old workaround for Simics - Fix indentation Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org> 
Remove support for obsolete hardware and cleanup.

- Remove checks for non integrated APICs
- Replace apic_write_around with apic_write.
- Remove apic_read_around
- Remove APIC version reads used by old workarounds
- Remove old workaround for Simics
- Fix indentation

Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>