When building some xtensa config, I hit the following warning:
  drivers/staging/mt7621-dts/Kconfig:4:warning: 'BUILTIN_DTB' has wrong type.
  'select' only accept arguments of bool and tristate type

It is due to some arch use BUILTIN_DTB as a flag for the need to builtin
dtb but xtensa use it as a string for which dtb to bulltin.
But for this (which dtb to build), it is better to use
BUILTIN_DTB_SOURCE like other arch do.

Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

Secondary CPU reset vector overlaps part of the double exception handler
code, resulting in weird crashes and hangups when running user code.
Move exception vectors one page up so that they don't clash with the
secondary CPU reset vector.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

There is no good reason to duplicate the PCI menu in every architecture.
Instead provide a selectable HAVE_PCI symbol that indicates availability
of PCI support, and a FORCE_PCI symbol to for PCI on and the handle the
rest in drivers/pci.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Acked-by: Max Filippov <jcmvbkbc@gmail.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Paul Burton <paul.burton@mips.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Now that noMMU cache attributes are set up separately drop no longer
used macro PLATFORM_DEFAULT_MEM_SIZE and config symbol
CONFIG_DEFAULT_MEM_SIZE used for setting it.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

Marking default memory region as cached is not always sufficient and is
not flexible. Allow specifying cache attributes for the whole memory
address space with new config entry MEMMAP_CACHEATTR. Apply it after
cache initialization.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

CONFIG_IRQ_DOMAIN_DEBUG is similar to CONFIG_GENERIC_IRQ_DEBUGFS,
just with less information.

Spring cleanup time.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Yang Shunyong <shunyong.yang@hxt-semitech.com>
Link: https://lkml.kernel.org/r/20180117142647.23622-1-marc.zyngier@arm.com

Now that memory initialization doesn't add default memory region
specify it explicitly in the memmap command line option in case somebody
wants to boot in non-DT-enabled configuration.

While at it update earlycon access mode to mmio32native to support both
LE and BE cores transparently.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

Now that memory initialization doesn't add default memory region specify
it explicitly in the memmap command line option.

Save common_defconfig as defconfig so that it doesn't have all option
settings in it, only those that are different from the Kconfig defaults.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

Now that memory initialization doesn't add default memory region specify
it explicitly in the memmap command line option.

Save iss_defconfig as defconfig so that it doesn't have all option
settings in it, only those that are different from the Kconfig defaults.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

Added defconfig, device tree and Xtensa variant header files for the
Cadence Configurable System Platform "xt_lnx" processor configuration.

Signed-off-by: Scott Telford <stelford@cadence.com>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>