linux-toradex.git/arch/xtensa/include/asm/pgtable.h, branch v4.2.7

mm: make FIRST_USER_ADDRESS unsigned long on all archs

2015-02-12T01:06:03+00:00

LKP has triggered a compiler warning after my recent patch "mm: account
pmd page tables to the process":

    mm/mmap.c: In function 'exit_mmap':
 >> mm/mmap.c:2857:2: warning: right shift count >= width of type [enabled by default]

The code:

 > 2857                WARN_ON(mm_nr_pmds(mm) >
   2858                                round_up(FIRST_USER_ADDRESS, PUD_SIZE) >> PUD_SHIFT);

In this, on tile, we have FIRST_USER_ADDRESS defined as 0.  round_up() has
the same type -- int.  PUD_SHIFT.

I think the best way to fix it is to define FIRST_USER_ADDRESS as unsigned
long.  On every arch for consistency.

Signed-off-by: Kirill A. Shutemov 
Reported-by: Wu Fengguang 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

xtensa: drop _PAGE_FILE and pte_file()-related helpers

2015-02-10T22:30:33+00:00

We've replaced remap_file_pages(2) implementation with emulation.  Nobody
creates non-linear mapping anymore.

Signed-off-by: Kirill A. Shutemov 
Acked-by: Max Filippov 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

xtensa: nommu: provide _PAGE_CHG_MASK definition

2014-10-21T09:28:46+00:00

Signed-off-by: Max Filippov

xtensa: implement pgprot_noncached

2014-10-05T23:23:50+00:00

The default pgprot_noncached doesn't do anything. This leads to issues
when drivers rely on it to disable caching in userspace mappings.
Implement pgprot_noncached properly so that caching of userspace mappings
could be controlled.

Signed-off-by: Max Filippov

xtensa: fix TLBTEMP_BASE_2 region handling in fast_second_level_miss

2014-08-14T07:59:19+00:00

Current definition of TLBTEMP_BASE_2 is always 32K above the
TLBTEMP_BASE_1, whereas fast_second_level_miss handler for the TLBTEMP
region analyzes virtual address bit (PAGE_SHIFT + DCACHE_ALIAS_ORDER)
to determine TLBTEMP region where the fault happened. The size of the
TLBTEMP region is also checked incorrectly: not 64K, but twice data
cache way size (whicht may as well be less than the instruction cache
way size).

Fix TLBTEMP_BASE_2 to be TLBTEMP_BASE_1 + data cache way size.
Provide TLBTEMP_SIZE that is a greater of doubled data cache way size or
the instruction cache way size, and use it to determine if the second
level TLB miss occured in the TLBTEMP region.

Practical occurence of page faults in the TLBTEMP area is extremely
rare, this code can be tested by deletion of all w[di]tlb instructions
in the tlbtemp_mapping region.

Cc: stable@vger.kernel.org
Signed-off-by: Max Filippov

xtensa: add HIGHMEM support

2014-04-06T17:29:21+00:00

Introduce fixmap area just below the vmalloc region. Use it for atomic
mapping of high memory pages.
High memory on cores with cache aliasing is not supported and is still
to be implemented. Fail build for such configurations for now.

Signed-off-by: Max Filippov

xtensa: use buddy allocator for PTE table

2013-11-15T00:32:19+00:00

At the moment xtensa uses slab allocator for PTE table.  It doesn't work
with enabled split page table lock: slab uses page->slab_cache and
page->first_page for its pages.  These fields share stroage with
page->ptl.

Signed-off-by: Kirill A. Shutemov 
Cc: Chris Zankel 
Acked-by: Max Filippov 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

Merge tag 'xtensa-next-20130710' of git://github.com/czankel/xtensa-linux

2013-07-11T19:30:33+00:00

Pull Xtensa updates from Chris Zankel.

* tag 'xtensa-next-20130710' of git://github.com/czankel/xtensa-linux: (22 commits)
  xtensa: remove the second argument of __bio_kmap_atomic()
  xtensa: add static function tracer support
  xtensa: Flat DeviceTree copy not future-safe
  xtensa: check TLB sanity on return to userspace
  xtensa: adjust boot parameters address when INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX is selected
  xtensa: bootparams: fix typo
  xtensa: tell git to ignore generated .dtb files
  xtensa: ccount based sched_clock
  xtensa: ccount based clockevent implementation
  xtensa: consolidate ccount access routines
  xtensa: cleanup ccount frequency tracking
  xtensa: timex.h: remove unused symbols
  xtensa: tell git to ignore copied zlib source files
  xtensa: fix section mismatch in pcibios_fixup_bus
  xtensa: ISS: fix section mismatch in iss_net_setup
  arch: xtensa: include: asm: compiling issue, need cmpxchg64() defined.
  xtensa: xtfpga: fix section mismatch
  xtensa: remove unused platform_init_irq()
  xtensa: tell git to ignore generated files
  xtensa: flush TLB entries for pages of non-current mm correctly
  ...

consolidate io_remap_pfn_range definitions

2013-06-29T08:46:35+00:00

Signed-off-by: Al Viro

xtensa: fix TLB multihit exceptions

2013-05-20T18:09:13+00:00

- set _PAGE_USER in the pte_clear to avoid having TLB multihit exceptions
  (see following threads for more details);
  http://lists.linux-xtensa.org/pipermail/linux-xtensa/Week-of-Mon-20130401/
  http://lists.linux-xtensa.org/pipermail/linux-xtensa/Week-of-Mon-20130408/
- improved documentation of the PTE layout
- fix PTE mapping for present and 'prot_none' pages for T1050 hw and earlier
- fix pte_file offset and size
- add check for the correct number of bits for swap type

CC: piet.delaney@gmail.com
CC: jcmvbkbc@gmail.com
Signed-off-by: Chris Zankel