linux-toradex.git/arch/xtensa/platforms/xtfpga, branch v4.9.11

xtensa: xtfpga: group platform_* functions together

2016-09-21T01:52:59+00:00

Group platform_* functions together and turn two separate #ifdef/#ifndef
blocks into single #ifdef/#else. No functional changes.

Signed-off-by: Max Filippov

xtensa: rearrange CCOUNT calibration

2016-09-21T01:52:59+00:00

DT-enabled kernel should have a CPU node connected to a clock. This clock
is the CCOUNT clock. Use old platform_calibrate_ccount call as a fallback
when CPU node cannot be found or has no clock and in non-DT-enabled
configurations.

Drop no longer needed code that updates CPU clock-frequency property in
the DT; drop DT-related code from the platform_calibrate_ccount too.

Move of_clk_init to the top of time_init, so that clocks are initialized
before CCOUNT calibration is attempted.

Signed-off-by: Max Filippov

xtensa: xtfpga: use clock provider, don't update DT

2016-09-21T01:52:51+00:00

Instead of querying hardcoded FPGA frequency register and then updating
clock-frequency property in specificly named DT nodes in machine setup
code register a clock provider that returns fixed-rate clock, configured
by register specified in DT. This way we have less magic/hardcoded names
and use more existing common clock framework code.

Signed-off-by: Max Filippov 
Tested-by: Guenter Roeck

xtensa: extract common CPU reset code into separate function

2016-09-12T06:53:22+00:00

platform_restart implementatations do the same thing to reset CPU.
Don't duplicate that code, move it to a function and call it from
platform_restart.

Signed-off-by: Max Filippov

xtensa: xtfpga: fix ethernet controller endianness

2016-03-11T08:53:31+00:00

Ethernet controller is attached to XTFPGA boards as native endian device,
mark it as such in DTS and pass correct endianness in platform data.
This makes network functional on big-endian CPUs.

Signed-off-by: Max Filippov

xtensa: xtfpga: fix serial port register width and endianness

2016-03-11T08:53:31+00:00

Serial port is attached to XTFPGA boards as native endian device, mark
it as such in DTS and pass correct endianness in platform data.
Set register width in DTS to 4, this way it matches the platform data
and works correctly on big-endian CPUs.

Signed-off-by: Max Filippov

xtensa: xtfpga: fix integer overflow in TASK_SIZE

2015-11-02T15:02:55+00:00

This fixes the following warning when default memory region crosses
0x80000000:

  arch/xtensa/include/asm/processor.h:40:47: warning:
    integer overflow in expression [-Woverflow]
    #define TASK_SIZE (PLATFORM_DEFAULT_MEM_START + PLATFORM_DEFAULT_MEM_SIZE)
                                               ^
Signed-off-by: Max Filippov

xtensa: fixes for configs without loop option

2015-11-02T15:02:47+00:00

Build-time fixes:
- make lbeg/lend/lcount save/restore conditional on kernel entry;
- don't clear lcount in platform_restart functions unconditionally.

Run-time fixes:
- use correct end of range register in __endla paired with __loopt, not
  the unused temporary register. This fixes .bss zero-initialization.
  Update comments in asmmacro.h;
- don't clobber a10 in the usercopy that leads to access to unmapped
  memory.

Cc: 
Signed-off-by: Max Filippov

Merge tag 'xtensa-for-next-20150413' of git://github.com/jcmvbkbc/linux-xtensa into for_next

2015-04-14T04:47:53+00:00

Xtensa improvements for 4.1:

- fix locking issues in ISS network driver;
- document PIC and MX interrupt distributor device tree bindings;
- add CY7C67300 USB controller support to XTFPGA.

Signed-off-by: Chris Zankel

xtensa: xtfpga: add CY7C67300 USB controller support

2015-04-13T06:34:37+00:00

Signed-off-by: Max Filippov