linux-toradex.git/arch, branch tegra-10.9.7 Linux kernel for Apalis and Colibri modules [tegra/odm_kit]: Update copyright notices 2010-12-01T01:53:22+00:00 Hoang Pham hopham@nvidia.com 2010-11-11T19:27:56+00:00 0fb1d22236e062c48a112d3cd0c1f6e6d90023a3 Bug 744290 (cherry picked from commit 82ac01fbbab3ede7ad5b841ff74bb73e309753b2) Reviewed-on: http://git-master/r/10603 (cherry picked from commit 0d5ab28a613a878ef7bd0d931002c07334e63802) Change-Id: Ic2053adcd1bc5c4012ddc2795f8d991b734c774e Reviewed-on: http://git-master/r/11281 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> 
Bug 744290
(cherry picked from commit 82ac01fbbab3ede7ad5b841ff74bb73e309753b2)
Reviewed-on: http://git-master/r/10603
(cherry picked from commit 0d5ab28a613a878ef7bd0d931002c07334e63802)

Change-Id: Ic2053adcd1bc5c4012ddc2795f8d991b734c774e
Reviewed-on: http://git-master/r/11281
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
[ARM/tegra] RM: Stopped DVFS in PM_SUSPEND_PREPARE. 2010-12-01T01:51:46+00:00 Alex Frid afrid@nvidia.com 2010-11-26T04:56:57+00:00 01a0b8146665a17dd063b4b8e2fe80e5bd795c22 Bug 760630 Change-Id: If5e4ac1045cdb46d12a03bf47f24fb712fdbd11e Reviewed-on: http://git-master/r/11632 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> 
Bug 760630

Change-Id: If5e4ac1045cdb46d12a03bf47f24fb712fdbd11e
Reviewed-on: http://git-master/r/11632
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
[ARM/tegra] RM: Disabled 3D power gating in LP1. 2010-12-01T01:44:18+00:00 Alex Frid afrid@nvidia.com 2010-11-25T04:12:06+00:00 a735cfb19d8e974fe4111b0686e78ebbb1bf43ca Bug 753226 Change-Id: I34e9e392580b38d4ebf805ce984a800097adf09a Reviewed-on: http://git-master/r/11527 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> 
Bug 753226

Change-Id: I34e9e392580b38d4ebf805ce984a800097adf09a
Reviewed-on: http://git-master/r/11527
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
[arm/tegra] Keep SDIO1 lines high on boot-up. 2010-11-30T03:55:49+00:00 Rahul Bansal rbansal@nvidia.com 2010-11-24T18:13:41+00:00 9b428890b27323d34a137ffa70a34a14a60fe7d7 Internally pulling up SDIO lines from AP side should eliminate the need of external SDIO pullups or dependency on wifi driver to do the same. Bug: 760178 Change-Id: I021f21c83a679a4f823c06f1927c6f2f85483e32 Reviewed-on: http://git-master/r/11489 Reviewed-by: Rahul Bansal <rbansal@nvidia.com> Tested-by: Rahul Bansal <rbansal@nvidia.com> Reviewed-by: Udaykumar Rameshchan Raval <uraval@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> 
Internally pulling up SDIO lines from AP side
should eliminate the need of external SDIO
pullups or dependency on wifi driver to do
the same.

Bug: 760178
Change-Id: I021f21c83a679a4f823c06f1927c6f2f85483e32
Reviewed-on: http://git-master/r/11489
Reviewed-by: Rahul Bansal <rbansal@nvidia.com>
Tested-by: Rahul Bansal <rbansal@nvidia.com>
Reviewed-by: Udaykumar Rameshchan Raval <uraval@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
[Tegra NvRm]: Tristate MCLK if mediaserver crash 2010-11-29T19:24:59+00:00 byan byan@nvidia.com 2010-11-09T20:37:37+00:00 1ce2f5538e754957fe2f888fbcbccba41c5a6fd6 for bug 728160 Tristate MCLK if mediaserver crash to save power. This is done by ref-tracking pinmux for MCLK. The change actually also tracks the other 2 external clock sources, so all external clocks are tracked and cleaned up upon user space application crash. Change-Id: Ie2bc40f680586c01a916abbe51c91a7eb2d1cb13 Reviewed-on: http://git-master/r/10451 Reviewed-on: http://git-master/r/11451 Reviewed-by: Bo Yan <byan@nvidia.com> Tested-by: Bo Yan <byan@nvidia.com> Reviewed-by: Venkata (Muni) Anda <vanda@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> 
for bug 728160

Tristate MCLK if mediaserver crash to save power. This is done by
ref-tracking pinmux for MCLK.

The change actually also tracks the other 2 external clock sources, so
all external clocks are tracked and cleaned up upon user space
application crash.

Change-Id: Ie2bc40f680586c01a916abbe51c91a7eb2d1cb13
Reviewed-on: http://git-master/r/10451
Reviewed-on: http://git-master/r/11451
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Venkata (Muni) Anda <vanda@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
video: tegra: nvmap: Clean whole L1 instead of VA cleaning 2010-11-24T23:18:45+00:00 vdumpa vdumpa@nvidia.com 2010-10-29T18:37:42+00:00 05074ac6ce18a61467ad6d5dd5e53d56725c8d58 For large allocations, cleaning each page of the allocation can take a significant amount of time. If an allocation that nvmap needs to clean or invalidate out of the cache is significantly larger than the cache, just flush the entire cache. bug 711478 and bug 744221 Revert "video: tegra: nvmap: perform cache maintenance for rw_handle" This reverts commit d963f09c3ebb2d690d266f8f607b4876acaf2ab1. Reviewed-on: http://git-master/r/10213 (cherry picked from commit 6469f378a596f0572035cd27a17851ea86b763c9) Change-Id: I1e514f505db860eb01d575a98f0f80c8794e8463 Reviewed-on: http://git-master/r/10497 Reviewed-by: Eric Werness <ewerness@nvidia.com> Reviewed-by: Markus Holtmanns <mholtmanns@nvidia.com> Tested-by: Markus Holtmanns <mholtmanns@nvidia.com> Reviewed-by: Janne Hellsten <jhellsten@nvidia.com> Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> 
For large allocations, cleaning each page of the allocation can
take a significant amount of time. If an allocation that nvmap needs
to clean or invalidate out of the cache is significantly larger than
the cache, just flush the entire cache.

bug 711478 and bug 744221

Revert "video: tegra: nvmap: perform cache maintenance for rw_handle"

This reverts commit d963f09c3ebb2d690d266f8f607b4876acaf2ab1.

Reviewed-on: http://git-master/r/10213
(cherry picked from commit 6469f378a596f0572035cd27a17851ea86b763c9)

Change-Id: I1e514f505db860eb01d575a98f0f80c8794e8463
Reviewed-on: http://git-master/r/10497
Reviewed-by: Eric Werness <ewerness@nvidia.com>
Reviewed-by: Markus Holtmanns <mholtmanns@nvidia.com>
Tested-by: Markus Holtmanns <mholtmanns@nvidia.com>
Reviewed-by: Janne Hellsten <jhellsten@nvidia.com>
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
[arm/tegra]dma: protecting the dma transfer count update 2010-11-24T23:17:05+00:00 Laxman Dewangan ldewangan@nvidia.com 2010-11-17T12:30:48+00:00 f2b1e18bc44cd6bf8e76d00a5f0fcb0d2b2e0995 When client asked for the dma transfer count, then the dma status register read and update is protected by the spin lock so that it should not be updated incorrectly. If client asked for transfer count between dma interrupt occurs and dma isr thread executed and repeat mode is selected then updating the transfer count at the time of calculating transfer count. bug 732197 bug 731403 Change-Id: Id112d5bea9c2f4a1fc4d329d5ce04eed477f1dfa Reviewed-on: http://git-master/r/11019 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Udaykumar Rameshchan Raval <uraval@nvidia.com> Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> 
When client asked for the dma transfer count, then the dma
status register read and update is protected by the spin lock
so that it should not be updated incorrectly.
If client asked for transfer count between dma interrupt occurs
and dma isr thread executed and repeat mode is selected then
updating the transfer count at the time of calculating transfer
count.

bug 732197
bug 731403

Change-Id: Id112d5bea9c2f4a1fc4d329d5ce04eed477f1dfa
Reviewed-on: http://git-master/r/11019
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Udaykumar Rameshchan Raval <uraval@nvidia.com>
Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
[arm/tegra] nvrm: open handle at postcore initialization. 2010-11-22T23:02:32+00:00 Laxman Dewangan ldewangan@nvidia.com 2010-11-22T07:36:20+00:00 164d4221875009fe179dda6679709ed8f7f9537e The rm handle is getting open in clock_init() which got called as arch_init time. Before this init, postcore init got called and it setup most of modules data and result as call of rm api without opening the rm handle. Adding code such that rm should be open at postcore init time and so all rm call should have proper rm handle. bug 759147 Change-Id: I0ce93c807c64eaef48f73007ff0f64a52c89590a Reviewed-on: http://git-master/r/11316 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> 
The rm handle is getting open in clock_init() which got called
as arch_init time. Before this init, postcore init got called
and it setup most of modules data and result as call of rm api
without opening the rm handle.

Adding code such that rm should be open at postcore init time and
so all rm call should have proper rm handle.

bug 759147

Change-Id: I0ce93c807c64eaef48f73007ff0f64a52c89590a
Reviewed-on: http://git-master/r/11316
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
[arm/tegra] serial: Support for break on console driver. 2010-11-22T22:53:41+00:00 Laxman Dewangan ldewangan@nvidia.com 2010-10-19T08:35:15+00:00 ff4d0279c458b724d273efd88ee87ff7caf48991 There is sysrq feature which works from console with sending break and then character. The console driver uses the 8250 driver. In tegra uart controller, after receiving break, it needs to clear the rx fifo by reading fifo till empty to receive the another break/character. Fixing this issue in 8250 driver. bug 697978 Change-Id: I4eb71a67bafc186ec9934fce164e28ad86fa0ace Reviewed-on: http://git-master/r/8736 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> 
There is sysrq feature which works from console with
sending break and then character.
The console driver uses the 8250 driver.
In tegra uart controller, after receiving break, it
needs to clear the rx fifo by reading fifo till empty
to receive the another break/character.
Fixing this issue in 8250 driver.

bug 697978

Change-Id: I4eb71a67bafc186ec9934fce164e28ad86fa0ace
Reviewed-on: http://git-master/r/8736
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
[arm/config] Ventana: Enable suspend for USB. 2010-11-19T22:32:06+00:00 Rakesh Bodla rbodla@nvidia.com 2010-11-10T08:48:58+00:00 6678b8e8e8a087955cf60f3dc84abd9b246c956f On Ventana Android, USB consumes high power in OS idle mode. Power consumption is reduced by enabling the suspend. Bug 746087 Change-Id: Ia7af9be9b91467034270e8d1e1d3e539b4c11a49 Reviewed-on: http://git-master/r/10483 Tested-by: Rakesh Bodla <rbodla@nvidia.com> Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com> Reviewed-by: Rakesh Bodla <rbodla@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> 
On Ventana Android, USB consumes high power in OS idle mode. Power consumption is
reduced by enabling the suspend.

Bug 746087

Change-Id: Ia7af9be9b91467034270e8d1e1d3e539b4c11a49
Reviewed-on: http://git-master/r/10483
Tested-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com>
Reviewed-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>