Removed 50MHz floor for MIPI PLL high speed output frequency. This floor kept MIPI PLL low speed output (= high speed output / 8) above DSI panel specification - bug 651446. Change-Id: Id1d3314b46896cc8f6fb48d238ffed01fd6b4e4a Reviewed-on: http://git-master/r/787 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Venkata (Muni) Anda <vanda@nvidia.com> Tested-by: Venkata (Muni) Anda <vanda@nvidia.com>
Changed the registration to use the device ID same as instance. With this change instance 0 will show up as ttyHS0 and instance 1 will show up as ttyHS1 and so on. Before this change, if the instance 0 was not used on a platform, instance 1 would have showed up as ttyHS0. Bug 656451 Tested with Harmony. Made sure that all nodes showup in the device list except the missing instance. Change-Id: Ib4e04b12f16002deb899b38630de102c24e588b0 Reviewed-on: http://git-master/r/735 Reviewed-by: Ramachandrudu Kandhala <rkandhala@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
tegra 2 systems have a hardware errata which causes bit 20 of the TLS register (CP15 c13, operations 2-4) to be unreliable. in common user space threading libraries (glibc pthreads, bionic pthreads), the value stored in this register is guaranteed to be at least word-aligned, leaving bit 0 free. the work-around for this hardware errata is storing bit 20 of the user space-provided TLS value into bit 0 of the register inside __set_tls, and restoring it in the get_tls helper. Change-Id: I06439378edc01dc897708e3298cd91b5721c6e50 Reviewed-on: http://git-master/r/779 Reviewed-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com> Reviewed-by: Arthur Spence <aspence@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
nvmap build fails when CONFIG_TEGRA_IOVMM is not selected. add stubs to allow that combination to work. Change-Id: Ie7e47a987feaeffd987996d11a594b2c8551311e Reviewed-on: http://git-master/r/785 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
Change-Id: I02aa2fd9d5a4faa830e838d2705ee81058fe001d Change-Id: I02aa2fd9d5a4faa830e838d2705ee81058fe001d Reviewed-on: http://git-master/r/750 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com> Tested-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
This condition check width[0] == 0xf is not need based on spec and it is causing second finger samples are ignored many times. Fixes bug 653317 Change-Id: I2ada2732f0c4965817a0ed1dca1b6351e01d256a Reviewed-on: http://git-master/r/769 Reviewed-by: Gary King <gking@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com>
Added support for the new Whistler PMU revision that preserves CPU voltage across LP2 (it will allow to enable core voltage scaling on E1109 processor boards). Change-Id: I0724414c5148f39b3c6fa4f0d3f84963231d2520 Reviewed-on: http://git-master/r/726 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
Save/Restore context works only for dedicated host. Earlier it was enabled even for OTG. This is corrected by modifying the check in nvddk_usbphy.c. Checking for host mode instead of "IsHostMode" flag. Bug 658225: USB host is not working on android/whistler USB port1 in OTG mode. Tested on : Whistler USB1 OTG + USB3 host Now OTG host is getting detected Change-Id: Ia5a1e0744074a6486d8853ea10f6c860b3abb4f3 Reviewed-on: http://git-master/r/741 Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com> Tested-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
previously, the task of managing RM-managed memory handles was split between nvos (OS page allocation), the RM (heap management for carveout & IRAM heaps, and handle life-time management), nvreftrack (abnormal process termination) and nvmap (user-space read/write/map of memory handles). this resulted in an opaque system that was wasteful of kernel virtual address space, didn't support CPU cache attributes for kernel mappings and couldn't fully unwind leaked handles (e.g., if the application leaked a pinned handle the memory might never be reclaimed). nvmap is now a full re-implementation of the RM memory manager, unifying all of the functionality from nvreftrack, nvos, nvmap and nvrm into one driver used by both user and kernel-space clients. add configs to control paranoid operation. when paranoid is enabled, every handle reference passed into the kernel is verified to actually have been created by nvmap; furthermore, handles which are not global (the GET_ID ioctl has not been called for it) will fail validation if they are referenced by any process other than the one which created them, or a super-user process (opened via /dev/knvmap). each file descriptor maintains its own table of nvmap_handle_ref references, so the handle value returned to each process is unique; furthermore, nvmap_handle_ref objects track how many times they have been pinned, to ensure that processes which abnormally terminate with pinned handles can be unwound correctly. as a compile-time option, fully-unpinned handles which require IOVMM mappings may be stored in a segmented (by size) MRU (most-recently unpinned) eviction cache; if IOVMM space is over-committed across multiple processes, a pin operation may reclaim any or all of the IOVMM areas in the MRU cache. MRU is used as the eviction policy since graphics operations frequently operate cyclically, and the least-recently used entry may be needed almost immediately if the higher-level client starts (e.g.) rendering the next frame. introduce a concept of "secure" handles. secure handles may only be mapped into IOVMM space, and when unpinned their mapping in IOVMM space will be zapped immediately, to prevent malicious processes from being able to access the handle. expose carveout heap attributes for each carveout heap in sysfs, under the nvmap device with sub-device name heap-<heap name> * total size * free size * total block count * free block count * largest block * largest free block * base address * name * heap usage bitmask carveout heaps may be split at run-time, if sufficient memory is available in the heap. the split heap can be (should be) assigned a different name and usage bitmask than the original heap. this allows a large initial carveout to be split into smaller carveouts, to reserve sections of carveout memory for specific usages (e.g., camera and/or video clients). add a split entry in the sysfs tree for each carveout heap, to support run-time splitting of carveout heaps into reserved regions. format is: <size>,<usage>,<name> * size should be parsable with memparse (suffixes k/K and m/M are legal) * usage is the new heap's usage bitmask * name is the name of the new heap (must be unique) carveout heaps are managed using a first-fit allocator with an explicit free list, all blocks are kept in a dynamically-sized array (doubles in size every time all blocks are exhausted); to reduce fragmentation caused by allocations with different alignment requirements, the allocator will compare left-justifying and right-justifying the allocation within the first-fit block, and choose the justification that results in the largest remaining free block (this is particularly important for 1M-aligned split heaps). other code which duplicated functionality subsumed by this changelist (RM memory manager, NvOs carveout command line parser, etc.) is deleted; implementations of the RM memory manager on top of nvmap are provided to support backwards compatibility bug 634812 Change-Id: Ic89d83fed31b4cadc68653d0e825c368b9c92f81 Reviewed-on: http://git-master/r/590 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
register the GART (for harmony & whistler) with IOVMM, to instantiate the IOVMM device node. Change-Id: I0d8eba7fd056e2c2db979abbc3ddd0bb650d4312 Reviewed-on: http://git-master/r/446 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>