linux-toradex.git/arch, branch v2.6.32.7

x86, msr/cpuid: Pass the number of minors when unregistering MSR and CPUID drivers.

2010-01-28T23:03:02+00:00

commit da482474b8396e1a099c37ffc6541b78775aedb4 upstream.

Pass the number of minors when unregistering MSR and CPUID drivers.

Reported-by: Dean Nelson 
Signed-off-by: Dean Nelson 
LKML-Reference: <20100127023722.GA22305@sgi.com>
Signed-off-by: Russ Anderson 
Signed-off-by: H. Peter Anvin 
Signed-off-by: Greg Kroah-Hartman

x86: Reenable TSC sync check at boot, even with NONSTOP_TSC

2010-01-28T23:02:52+00:00

commit 6c56ccecf05fafe100ab4ea94f6fccbf5ff00db7 upstream.

Commit 83ce4009 did the following change
If the TSC is constant and non-stop, also set it reliable.

But, there seems to be few systems that will end up with TSC warp across
sockets, depending on how the cpus come out of reset. Skipping TSC sync
test on such systems may result in time inconsistency later.

So, reenable TSC sync test even on constant and non-stop TSC systems.
Set, sched_clock_stable to 1 by default and reset it in
mark_tsc_unstable, if TSC sync fails.

This change still gives perf benefit mentioned in 83ce4009 for systems
where TSC is reliable.

Signed-off-by: Venkatesh Pallipadi 
Acked-by: Suresh Siddha 
LKML-Reference: <20091217202702.GA18015@linux-os.sc.intel.com>
Signed-off-by: H. Peter Anvin 
Signed-off-by: Greg Kroah-Hartman

KVM: x86: Fix leak of free lapic date in kvm_arch_vcpu_init()

2010-01-28T23:02:48+00:00

commit 443c39bc9ef7d8f648408d74c97e943f3bb3f48a upstream.

In function kvm_arch_vcpu_init(), if the memory malloc for
vcpu->arch.mce_banks is fail, it does not free the memory
of lapic date. This patch fixed it.

Signed-off-by: Wei Yongjun 
Signed-off-by: Marcelo Tosatti 
Signed-off-by: Greg Kroah-Hartman

KVM: x86: Fix probable memory leak of vcpu->arch.mce_banks

2010-01-28T23:02:47+00:00

commit 36cb93fd6b6bf7e9163a69a8bf20207aed5fea44 upstream.

vcpu->arch.mce_banks is malloc in kvm_arch_vcpu_init(), but
never free in any place, this may cause memory leak. So this
patch fixed to free it in kvm_arch_vcpu_uninit().

Signed-off-by: Wei Yongjun 
Signed-off-by: Marcelo Tosatti 
Signed-off-by: Greg Kroah-Hartman

KVM: x86: Fix host_mapping_level()

2010-01-28T23:02:46+00:00

commit 82b7005f0e72d8d1a8226e4c192cbb0850d10b3f upstream.

When found a error hva, should not return PAGE_SIZE but the level...

Also clean up the coding style of the following loop.

Signed-off-by: Sheng Yang 
Signed-off-by: Marcelo Tosatti 
Signed-off-by: Greg Kroah-Hartman

KVM: MMU: bail out pagewalk on kvm_read_guest error

2010-01-28T23:02:45+00:00

commit a6085fbaf65ab09bfb5ec8d902d6d21680fe1895 upstream.

Exit the guest pagetable walk loop if reading gpte failed. Otherwise its
possible to enter an endless loop processing the previous present pte.

Signed-off-by: Marcelo Tosatti 
Signed-off-by: Greg Kroah-Hartman

KVM: Fix race between APIC TMR and IRR

2010-01-28T23:02:44+00:00

commit a5d36f82c4f3e852b61fdf1fee13463c8aa91b90 upstream.

When we queue an interrupt to the local apic, we set the IRR before the TMR.
The vcpu can pick up the IRR and inject the interrupt before setting the TMR,
and perhaps even EOI it, causing incorrect behaviour.

The race is really insignificant since it can only occur on the first
interrupt (usually following interrupts will not change TMR), but it's better
closed than open.

Fixed by reordering setting the TMR vs IRR.

Signed-off-by: Avi Kivity 
Signed-off-by: Marcelo Tosatti 
Signed-off-by: Greg Kroah-Hartman

KVM: S390: fix potential array overrun in intercept handling

2010-01-28T23:02:40+00:00

commit 062d5e9b0d714f449b261bb522eadaaf6f00f438 upstream.

kvm_handle_sie_intercept uses a jump table to get the intercept handler
for a SIE intercept. Static code analysis revealed a potential problem:
the intercept_funcs jump table was defined to contain (0x48 >> 2) entries,
but we only checked for code > 0x48 which would cause an off-by-one
array overflow if code == 0x48.

Use the compiler and ARRAY_SIZE to automatically set the limits.

Signed-off-by: Christian Borntraeger 
Signed-off-by: Marcelo Tosatti 
Signed-off-by: Greg Kroah-Hartman

davinci: dm646x: Add support for 3.x silicon revision

2010-01-28T23:00:41+00:00

commit f63dd12da29f47c37bbc093abec098538e04357c upstream.

DM6467 silicon revisions 3.x have variant field in JTAGID register as '1'.
This path adds entry for the same in dm646x_ids to be able to boot on boards
with 3.x revision chips.

Also modifies name for 'variant=0' (revisions 1.0, 1.1).

Signed-off-by: Hemant Pedanekar 
Signed-off-by: Kevin Hilman 
Cc: Ben Hutchings 
Signed-off-by: Greg Kroah-Hartman

powerpc/fsl: Add PCI device ids for new QoirQ chips

2010-01-28T23:00:40+00:00

commit a3f62bd2b20c769ddc989b242ddd274179e19ee6 upstream by
Kumar Gala .  I have adjusted the patch
context for 2.6.32.

Signed-off-by: Kumar Gala 
Signed-off-by: Ben Hutchings 
Signed-off-by: Greg Kroah-Hartman