Pull ARM SoC fixes from Arnd Bergmann:
 "Not much interesting going on fixes-wise for us this week, as it
  should be for an -rc7.  I'm not expecting Olof to work much over
  Thanksgiving weekend, so I decided to take over again and push these
  out to you.

  Just four simple fixes this week:

   - one missing of_node_put() on armv7 based mvebu
   - forcing the USB host into the right mode on Chromebook
     (exynos5-snow)
   - enabling two important drivers for exynos_defconfig
   - fixing a noncritical bug for tegra that would cause a regression
     with common code patches queued for 3.19"

* tag 'armsoc-for-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: tegra: irq: fix buggy usage of irq_data irq field
  ARM: exynos_defconfig: Enable max77802 rtc and clock drivers
  ARM: dts: Explicitly set dr_mode on exynos5250-snow
  ARM: mvebu: add missing of_node_put() call in coherency.c

Pull ARM fixes from Russell King:
 "Another round of relatively small ARM fixes.

  Thomas spotted that the strex backoff delay bit was a disable bit, so
  it needed to be clear for this to work.  Vladimir spotted that using a
  restart block for the cache flush operation would return -EINTR, which
  userspace was not expecting.  Dmitry spotted that the auxiliary
  control register accesses for Xscale were not correct"

* 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm:
  ARM: 8226/1: cacheflush: get rid of restarting block
  ARM: 8222/1: mvebu: enable strex backoff delay
  ARM: 8216/1: xscale: correct auxiliary register in suspend/resume

Pull mips fixes from Ralf Baechle:
 "The hopefully final round of fixes for 3.18:

   - Fix a number of build errors affecting particular configurations.
   - Handle EVA correctly when flushing a signal trampoline and dcache
     lines.
   - Fix printks printing jibberish.
   - Handle 64 bit memory addresses correctly when adding memory chunk
     on 32 bit kernels.
   - Fix a race condition in the hardware tablewalker code"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
  MIPS: tlbex: Fix potential HTW race on TLBL/M/S handlers
  MIPS: Fix address type used for early memory detection.
  MIPS: Kconfig: Don't allow both microMIPS and SmartMIPS to be selected.
  MIPS: kernel: cps-vec: Set ISA level to mips32r2 for the MIPS MT ASE
  MIPS: Netlogic: handle modular AHCI builds
  MIPS: Netlogic: handle modular USB case
  MIPS: Loongson: Make platform serial setup always built-in.
  MIPS: fix EVA & non-SMP non-FPU FP context signal handling
  MIPS: cpu-probe: Set the FTLB probability bit on supported cores
  MIPS: BMIPS: Fix ".previous without corresponding .section" warnings
  MIPS: uaccess.h: Fix strnlen_user comment.
  MIPS: r4kcache: Add EVA case for protected_writeback_dcache_line
  MIPS: Fix info about plat_setup in arch_mem_init comment
  MIPS: rtlx: Remove KERN_DEBUG from pr_debug() arguments in rtlx.c
  MIPS: SEAD3: Fix LED device registration.
  MIPS: Fix a copy & paste error in unistd.h

Pull powerpc fixes from Michael Ellerman:
 "Here are five fixes for you to pull please.

  They're all CC'ed to stable except the "Fix PE state format" one which
  went in this release"

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mpe/linux:
  powerpc: 32 bit getcpu VDSO function uses 64 bit instructions
  powerpc/powernv: Replace OPAL_DEASSERT_RESET with EEH_RESET_DEACTIVATE
  powerpc/eeh: Fix PE state format
  powerpc/pseries: Fix endiannes issue in RTAS call from xmon
  powerpc/powernv: Fix the hmi event version check.

Pull sparc fixlet from David Miller:
 "Aparc fix to add dma_cache_sync(), even if a nop it should be provided
  if dma_{alloc,free}_noncoherent() is provided too"

* git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc:
  sparc: Add NOP dma_cache_sync() implementation.

There is a potential race when probing the TLB in TLBL/M/S exception
handlers for a matching entry. Between the time we hit a TLBL/S/M
exception and the time we get to execute the TLBP instruction, the
HTW may have replaced the TLB entry we are interested in hence the TLB
probe may fail. However, in the existing handlers, we never checked the
status of the TLBP (ie check the result in the C0/Index register). We
fix this by adding such a check when the core implements the HTW. If
we couldn't find a matching entry, we return back and try again.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Cc: <stable@vger.kernel.org> # v3.17+
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8599/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

We cannot restart cacheflush safely if a process provides user-defined
signal handler and signal is pending. In this case -EINTR is returned
and it is expected that process re-invokes syscall. However, there are
a few problems with that:
 * looks like nobody bothers checking return value from cacheflush
 * but if it did, we don't provide the restart address for that, so the
   process has to use the same range again
 * ...and again, what might lead to looping forever

So, remove cacheflush restarting code and terminate cache flushing
as early as fatal signal is pending.

Cc: stable@vger.kernel.org # 3.12+
Reported-by: Chanho Min <chanho.min@lge.com>
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Under extremely rare conditions, in an MPCore node consisting of at
least 3 CPUs, two CPUs trying to perform a STREX to data on the same
shared cache line can enter a livelock situation.

This patch enables the HW mechanism that overcomes the bug. This fixes
the incorrect setup of the STREX backoff delay bit due to a wrong
description in the specification.

Note that enabling the STREX backoff delay mechanism is done by
leaving the bit *cleared*, while the bit was currently being set by
the proc-v7.S code.

[Thomas: adapt to latest mainline, slightly reword the commit log, add
stable markers.]

Fixes: de4901933f6d ("arm: mm: Add support for PJ4B cpu and init routines")

Cc: <stable@vger.kernel.org> # v3.8+
Signed-off-by: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Pull "mvebu fixes for v3.18 (round 2)" frm Jason Cooper:

 - mvebu
    - coherency.c needed an of_node_put()

* tag 'mvebu-fixes-3.18-2' of git://git.infradead.org/linux-mvebu:
  ARM: mvebu: add missing of_node_put() call in coherency.c

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Pull "Samsung defconfig update for v3.18" from Kukjin Kim:

- enable max77802 rtc and clock drivers for exynos_defconfig
  : enable the kernel config options to have the drivers for
    max77802 including rtc and 2-ch 32kHz clock outputs

* tag 'samsung-defconfig-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  ARM: exynos_defconfig: Enable max77802 rtc and clock drivers

Signed-off-by: Arnd Bergmann <arnd@arndb.de>